LMH1983: Issues with PLL1 GenLocking

Hi Miguel,

There could be a loop filter capacitor issue or register configuration issue. Please check if below links can help you.

https://e2e.ti.com/support/interface-group/interface---internal/f/interface---internal-forum/307919/lmh1983-behavior-freerun-to-genlock?tisearch=e2e-sitesearch&keymatch=lmh1983#

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/337248/lmh1983-nolock-issue-request-technical-support?tisearch=e2e-sitesearch&keymatch=lmh1983#

https://e2e.ti.com/support/interface-group/interface---internal/f/interface---internal-forum/341334/lmh1983---lock_threshold-register-question?tisearch=e2e-sitesearch&keymatch=lmh1983#

https://e2e.ti.com/support/interface-group/interface---internal/f/interface---internal-forum/293484/lmh1983-nolock-noalign-indication?tisearch=e2e-sitesearch&keymatch=lmh1983#

https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/268598/lmh1983---trs-crc-errors-in-freerun-mode?tisearch=e2e-sitesearch&keymatch=lmh1983#

https://e2e.ti.com/support/interface-group/interface---internal/f/interface---internal-forum/302990/lmh1983-no_ref-status?tisearch=e2e-sitesearch&keymatch=lmh1983#

https://e2e.ti.com/support/interface-group/interface---internal/f/interface---internal-forum/337273/lmh1983-configuration?tisearch=e2e-sitesearch&keymatch=lmh1983#

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/154877/lmh1983-nolock-indication/1188238?tisearch=e2e-sitesearch&keymatch=lmh1983#1188238

https://e2e.ti.com/support/interface-group/interface---internal/f/interface---internal-forum/341334/lmh1983---lock_threshold-register-question?tisearch=e2e-sitesearch&keymatch=lmh1983#

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/551828/lmh1983---loss-of-lock-loss-of-reference-detection?tisearch=e2e-sitesearch&keymatch=lmh1983#

Hello Noel, 

Just to clarify, the capacitors that you are referring to are the ones that connect to VC_LPF (Pin40)? I have the recommended values from the reference design.

Also, we are noticing that it locks sometimes, but as soon as we do the next read, its unlocked. 

Hi Miguel,

Right, the big one, 47µF. Leakage current in the capacitor will also create unlock issue.

FYI, in the eval board, we were using this capacitor:  293D476X9010B2TE3. 

Noel, 

after reviewing the capacitors, the one that I am using has significant higher ESR and tolerance of 20%, which is high. 

It seems that I might have found the issue with my situation. There is an impedance mismatch between my input sync source and design, which is causing jitter. However, after I fixed the mismatch, PLL1 was still not locking. I went ahead and changed the Lock Step Size register (0x2D) to 01. After that, PLL1 began to Lock. However, since I still need to modify the register, I'm thinking it has to do with the low-quality capacitor I am using.