Part Number: LMK04828
Tool/software:
I am currently debugging the development board with 3 AD9695 (namely A, B, and C) and 1 lmk04828 clock chip. The lmk04828 chip operates in Cascaded Zero-Delay Dual-Loop Mode, and the sysref is continuously generated. In the Verilog program, the same JESD204 RX IP core is used (default SYSREF always for SYSREF always on). By adjusting the delay of the declk and sysref, I am able to align the rx_tvalid output from the RX IP core in the same core clock cycle.
However, according to the results, AC sampling data is synchronized, but AB is not. The figure below shows the results of AB and AC sampling the same sine wave.
Could this be related to the setup and hold state of sysref in the AD9695 registers (0x128, 0x129)? Or are there any references for multi-chip synchronization schemes?
