LMK03328: Appropriate clock devices for recovery clock from FPGA SerDes

Tool/software:

Dear Technical Support Team,

I have been looking into the clock generator and jitter cleaner.

Input recovery clock from AMD FPGA SerDes.

Input clock (recovery clock): LVDS 100MHz

Output clock: LVDS 200MHz x2 (1 free-run output, 1 PLL output)

Q1.

Can LMK03328 input recovery clock ? It has not clean. 

According to the following app note, it describes that narrow-loop bandwidth loop filter can clean jitter.

Can a clock generator act as a jitter cleaner?

Q2.

Do you have any recoomended clock device for clock generator an Jitter cleaner?

Required clock is only 2 output, so for example,LMK04828, LMK04832, LMK05318 seeems to be an over specification.

CDCE62002: SERDES Jitter Clearner: How it works? - Clock & timing forum - Clock & timing - TI E2E support forums

Best Regards,

ttd