LMH1983 lock issue

We are using LMH1983 clock generator in one of our video projects. We are facing an issue related to lock de-assertion. The LMH1983 loses lock whenever we externally switch the HVF (input to LMH1983) to another HVF of same format(1080p24), derived from the same source(same ppm) but with a different phase delay (80 sample delay difference). These HVFs are digital HVFs derived from FPGA serdes.
We are following below configuration sequence,
   1) write reg 0x05 with 0x80   (soft reset)
   2) write reg 0x09 with 0x02   (Power up initialization)
   3) write reg 0x09 with 0x00   (Power up initialization)
   4) write reg 0x06 with 0x07   (Polarity of Fsync, Vsync and Hsync is active high)
   5) write reg 0x0A with 0x99   (Clock2, Clock3, Fout2 & Fout3 are enabled)
   6) write reg 0x11 with 0x04
   7) write reg 0x12 with 0x00
   8) write reg 0x13 with 0x00
   9) write reg 0x34 with 0x28   (PLL4 disabled)
   10) Wait till NO_LOCK to go low
   11) read reg 0x20
   12) write reg 0x07/0x08 with Output Format
   13) write reg 0x09 with Crosspoint value
   (Steps 1 to 9 are followed only on power up, but steps 10 to 13 are followed each time LMH1983
    loses lock)

We have following questions,    
1)Is our understanding correct that the LMH1983 will not lose lock when HVF inputs are switched externally between HVFs of same format and from the same source, but with the phase difference? If yes, please tell us the correct configuration sequence to be followed.
2)In the question-1, what happens to LMH1983 lock if we switch between HVFs of same format but from different sources(with difference in ppm)?