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LMK05318B: DPLL: Enable or Disable BAW Frequency Lock Detect?

Quint Underwood
Intellectual 380 points
Part Number: LMK05318B


Tool/software:

Hello,

Based on the notes in TICS Pro (v1.7.7.10), I see recommendations to DISABLE the BAW Frequency Lock Detect when the DPLL is in use. Can you confirm that this is correct?

(I presume this is because when DPLL is active, it's responsible for the steering of the 2.5GHz BAW oscillator? And this means the BAW frequency lock detect is not needed for some reason?)

The reason for confusion is that the 1PPS default configuration has DPLL enabled, as well as the BAW Frequency Lock Detect. I had been assuming that this 1PPS default configuration is a safe/validated starting point for any design. It's concerning if this is not the case.

Thank you.

  • +1
    TI__Genius 16745 points

    Hi Quint,

    You are on the right track with your understanding. I need to clarify that description in the GUI because it is OK to enable BAW_LOCK when the DPLL is enabled. However, it is not recommended to use the BAW_LOCK status signal when the DPLL is locked for the following reasons:

    • BAW_LOCK detector indicates if APLL1 (BAW VCO or VCBO) has locked to the XO input.
    • When BAW_LOCK reports 0...
      • The VCBO is considered to be locked if the frequency error between the BAW and the XO input is within the BAW Frequency Lock Detect lock threshold defined by register setting.
    • When BAW_LOCK reports 1...
      • The VCBO is considered to be unlocked if the frequency error exceeds the BAW Frequency Lock Detect unlock threshold register setting.
    • Consider an example case where the XO input has a ± 50 ppm accuracy, the REF input has a ± 1 ppm accuracy, and the BAW lock detect register setting is configured to a 5 ppm lock threshold and 10 ppm unlock threshold.
      • When the device is in holdover or free-run mode, the VCBO is locked to XO input and the frequency error between the VCBO and XO input is near 0 ppm. BAW_LOCK = 0 since the error between the VCBO and XO is less than the 5 ppm lock setting.

      • Once a valid DPLL input (PRIREF/SECREF) is present, the DPLL is active and attempts to lock to PRIREF/SECREF. When the DPLL is locked, the VCBO is phase and frequency locked to PRIREF/SECREF. The frequency error between the VCBO and PRIREF/SECREF is near or approaching 0 ppm as the DPLL continuously tracks the phase of PRIREF/SECREF and makes corrections to the APLL numerator.
      • It is possible that at one point the XO input deviates + 20 ppm, for example, while the DPLL is locked. This means the frequency error between PRIREF/SECREF and the XO input is + 20 ppm (if we assume the PRIREF/SECREF input is 0 ppm) which, therefore, means the frequency error between the VCBO and the XO input is + 20 ppm. Therefore, BAW_LOCK = 1 because the error between the VCBO and the XO input exceeds the 10 ppm unlock setting.

    Does this answer your question?

    Regards,

    Jennifer