LMK04832: Clock distribution 10Mhz with 156.25MHz output

Ivan Intermite

Part Number: LMK04832

Tool/software:

Hello experts,

I am looking for support for the configurations of my RSOCs in my project. in particular I would like to configure my LMK04832 into a 10MHz. all the clocks go to the kintex ultrascale FPGA into LVDS format. The output required are the following:

2x 156.25Mhz for the GTH banks.
2x 125Mhz
250Mhz x 1 DDR4 clocks
100Mhz x 3

we can choose any external VCXO. using your tools the configurations recommended was the following.
the only clocks that mandatorily require PLL2 from the 10MHz are the 125MHhz and 250Mhz clocks.

however when we tried to create the configurations with tics pro we failed to reproduce this configurations created on your website.
can you please advise?

5 months ago

0 vicente flores prado 5 months ago

TI__Mastermind 28982 points

Hello Ivan,
We have the frequency planner to assist with this but otherwise it's as follows:

If you can use a 156.25MHz VCXO we can double this to maximize the PFD frequency and reduce the N divider to get a 3dB improvement in the PLL flat noise region.
The 2500MHz VCO frequency will be divided down to cerate the required outputs.
Do you require and type of input-to-output phase determinism?

I don't know which outputs you want where so you can edit the output dividers as needed for your application.

10MHz In 156p25MHz VCXO 2500MHz VCO.tcs

Best regards,

Vicente

0 Ivan Intermite 5 months ago in reply to vicente flores prado

Prodigy 20 points

thank you I will try in the next days and I will update you.

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LMK04832: Clock distribution 10Mhz with 156.25MHz output