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LMK04832: Output Clocks Not Phase Aligned after adjusting Output Clock Divider

Part Number: LMK04832


Tool/software:

Hi All,


Attempting to update the DCLKX_Y_DIV register after the initial configuration results in the output clock being misaligned. 

Our configuration has the PLL in dual loop mode, feeding a 3GHz device clock to the output clock dividers. Our initial configuration has these dividers set to 24 & 30 providing 100MHz & 125MHz with DDLY in powerdown. Ideally, our output clocks would be phase aligned to the input clock (ClkIn0/1). Upon modifying the DCLKX_Y_DIV register, we noticed the output clocks are not aligned with each other.

We attempted to perform a SYNC, but still noticed a large phase offset after modifying the DCLKX_Y_DIV register.

Our process to update the output clock is as follows:

  1. Update DCLKX_Y_DIV
  2. Update DCLKX_Y_DDLY
  3. DCLKX_Y_DDLY_PD = 0
  4. SYNC_DISX = 0
  5. Set SYNC_MODE = 1 & SYNC_1SHOT_EN = 1
  6. Toggle SYNC_POL, wait 100ms, Toggle SYNC_POL
  7. SYNC_DISX = 1
  8. DCLKX_Y_DDLY_PD = 1
  9. Update DCLKX_Y_FMT

Note, the DDLY and DIV for each modified clock is the same. for example: DCLK2 & DCLK7 have DIV = 15, DDLY = 15. We originally attempted only updating DCLKX_Y_DIV but ran into the same misalignment.

Can someone help us understand what we have misconfigured to get this result? Or are we simply missing a sync operation?

I've attached the register map of PLL initial configuration.

000080
000000
010018
01010A
010210
010340
010410
010500
010601
010711
010818
01090A
010A10
010B40
010C10
010D00
010E01
010F11
01101E
01110B
011210
011340
011410
011500
011601
011710
01181E
01190A
011A10
011B40
011C00
011D00
011E01
011F11
012018
01210A
012210
012340
012410
012500
012601
012711
012818
01290A
012A10
012B40
012C10
012D00
012E01
012F11
013018
01310A
013210
013340
013410
013500
013601
013711
013820
013900
013A0C
013B00
013C00
013D08
013E03
013F00
01400B
014100
014200
014310
014400
014500
01469A
01470A
014810
014950
014A00
014B11
014C00
014D00
014EC0
014F14
015030
015100
01520A
015300
015402
015500
015602
015700
015801
015900
015A02
015BD4
015C20
015D00
015E1E
015F23
016000
016101
0162AD
016300
016400
01650C
016958
016A20
016B00
016C00
016D00
016E1B
017310
017700
018200
018300
016600
016700
01681E
055500

  • Hi Grant,

    Can you try setting SYNC_1SHOT_EN = 0? Additionally, have you set SYNC_EN = 1?

    Also, how are you issuing the commands to the device? When using TICS Pro, the divider SYNC operation is triggered with the following sequence of commands:

    0x10200

    0x14480

    0x10A00

    0x11200

    0x11A00

    0x12200

    0x12A00

    0x13200

    0x14081

    0x14400

    0x13900

    0x14319

    0x14339

    0x14319

    0x10420

    0x10C20

    0x11420

    0x11C20

    0x12420

    0x12C20

    0x13420

    Thanks,

    Michael

  • Hi Michael,

    Thanks for the reply. There was no change with SYNC_OneShot Disabled, and we do have Sync_Enabled set True. 

    We are configuring the PLL via 3-wire SPI from an FPGA based microprocessor, the board performs an initial setup and later a secondary config alters the div / ddly registers as mentioned in our first message. 

    Having done some more reading, we determined we actually require a 0-delay configuration. Our end goal is to have the CLKout, External VCXO (OscIn for PLL2), and ClkInX to be phase aligned. We have attempted to set the PLL into dual-loop 0-delay nested + cascaded without any luck. 

    I have attached our TICS PRO if you don't mind confirming if we are missing a step? Note, we notice that it is never aligned. This includes the initial config or after update divider with the secondary configuration.

    Thanks again!
    7750.lmk04832.tcs

  • Hi Grant,

    The config looks good, but I will take this into lab on Monday and see if I can replicate your issue on one of our boards.

    Thanks,

    Michael