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CDCM6208: DCM6208 PLL repeatedly locking and unlocking – Need help understanding cause

Part Number: CDCM6208

Tool/software:

Hello TI Team,

I'm working with the CDCM6208 in a clock distribution design, and I'm observing a strange behavior: the PLL intermittently locks and then unlocks repeatedly during operation. The PLL_UNLOCK pin toggles between high and low over time, indicating the PLL is entering and exiting the lock state in a loop.

Here are the details of my configuration:

Register 0: 01B7
Register 1: 0060
Register 2: 02CD
Register 3: 00F0
Register 4: 30AB
Register 5: 0001
Register 6: 0016
Register 7: 0001
Register 8: 0016
Register 9: 0203
Register 10: 00A7
Register 11: 1C72
Register 12: 0001
Register 13: 0160
Register 14: 0000
Register 15: 0051
Register 16: 0160
Register 17: 0000
Register 18: 0051
Register 19: 0160
Register 20: 0000
Register 21: 0000
Register 40: 0000
Inputs:
Primary Input Frequency: 25
Secondary Input Frequency: 25
Version 1
C1: 100p
R2: 500
C2: 22n
R3: 100
C3: 242.5p
Charge Pump: 2m

STATUS0 :

  • Yang,

    A few questions and comments regarding your issue:

    - Can you confirm your external loop filter components? The ini. file says that C1=100p, R2=500, C2=22n is being used. Is that correct?

    - From using your config with C1=100p, R2=500, C2=22n, my device has no issue locking and does not show any STATUS0 signal toggling.

    - Can you send a scope plot of the input clock?

    - What is the timescale of the STATUS0 plot you shared? Does this issue happen with every powerup? Does the STATUS0 signal toggle forever or only a certain amount of time?

    - Does toggling the Calibration bit help at all?

    Best,

    Cris

  • I am using C1=100p, R2=510 C2=15n, and STATUS0 signal toggle forever

    This is the input frequency(LVCMOS):


    CDCM6208 EVM Software:

  • Is there any documented difference between CDCM6208V1RGZT and CDCM6208V2RGZT? Can their circuits be used interchangeably?

  • Yang,

    CDCM6208V1 and CDCM2108V2 have different VCO frequencies, and as such are not able to be used interchangeably.

    The waveform that you provided is the LVCMOS input? What is sourcing this? Is it properly terminated (some drivers have an output impedance other than 50 Ohms and require additional series termination resistors at the driver output).

    Thanks,

    Kadeem

  • I have successfully resolved the issue of the PLL repeatedly locking and unlocking by using the CDCM6208 V1 version.

    Now, I need to migrate to the V2 version of the CDCM6208.
    I am still using a 25 MHz LVCMOS input as the reference clock, and I have not changed the basic hardware design except for updating the Loop Filter components:
    I modified C1 to 200 pF, R2 to 400 Ω, and C2 to 22 nF.

    However, with these settings, the PLL cannot achieve a stable lock on the V2 device.
    The LOCK signal only pulls high briefly for a few seconds after startup, and then stays low continuously afterward.

    Could you please advise what adjustments I should make to achieve a stable lock with the V2 version under these conditions?


    Here are the details of my configuration:

    Register 0: 01B9
    Register 1: 0000
    Register 2: 0018
    Register 3: 00F5
    Register 4: 30AB
    Register 5: 0023
    Register 6: 0004
    Register 7: 0023
    Register 8: 0013
    Register 9: 0201
    Register 10: 0017
    Register 11: 5254
    Register 12: 0201
    Register 13: 0003
    Register 14: A92A
    Register 15: 0001
    Register 16: 0040
    Register 17: 0000
    Register 18: 0619
    Register 19: 0011
    Register 20: 26E9
    Register 21: 0000
    Register 40: 0000
    Inputs:
    Primary Input Frequency: 25
    Secondary Input Frequency: 25
    Version 2
    C1: 200p
    R2: 400
    C2: 22n
    R3: 100
    C3: 242.5p
    Charge Pump: 2.5m

  • Yang,

    Let us take a look at this on an evaluation module. Expect a response by tomorrow.

    Thanks,
    Kadeem

  • Yang,

    As Kadeem said, we will take a look at this on the bench tomorrow. In the meantime, can you try with the below configuration?

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/48/3630.DCM6208_5F00_CDCM6208_5F00_Settings_5F00_Test.ini

    Best,

    Cris

  • Yang,

    We found that the attached configuration worked on the bench. But I have a few questions:

    - Are you using the EVM?

    -If so, has the board been reworked to accept an LVCMOS input instead of a XTAL?

    - Ensure that the REF_SEL pin is configured for the correct input

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/48/April20_2D00_CDCM6208V2_5F00_Settings.ini

    Best,

    Cris