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LMKDB1108: LOS# not going low when input clock removed

Kevin Guy
Prodigy 20 points
Part Number: LMKDB1108

Tool/software:

Hello,

I have a design using the LMKDB108Z100RKPT and I cannot get the LOS# on pin 1 to go low when I remove the Clock Input. 

Here is the setup:

1) VDDA is at 3.3V,

2) The PWRGD/PWRDN# (pin 12) is at 3.3V,

3) The SLEWRATE_SEL is pulled to 3.3V through 4.75K resistor.

4) The OE# (Output Enable) for CLK0, CLK1, CLK2, and CLK3  on pins 14, 19,21, and 27 are all pulled low.

5) The Output Enable bits in Reg0 and Reg1 for CLK0, CLK1, CLK2, and CLK3  are programmed high. 

5) The LOS# on pin 1 is pulled up to 3.3V through a 4.75K ohm resistor.

I provide an a differential input clock that is close to 1400mVp-p on the CLKIN_P (pin 8) and CLKIN_N(pin 9) inputs.  The clock outputs of the LMKDB1108 show 1300mVp--p differential clocks on CLK0, CLK1, CLK2 and CLK3 pins. The LOS# (Pin 1) is high (pulled to 3.3V through a 4.75K ohm resistor).  I remove the differential Clock input and let the Clock_P and CLOCK_N inputs just float (They each have a 750mV DC bias).  When I remove the differential Clock Input, all the output clocks stop.  I expected the LOS# on pin 1 to go low, however, it remained at 3.3V (Through the 4.75K ohm pull-up to 3.3V). Any help would be appreciated.  Thanks in advance. 

  • 0
    TI__Genius 9190 points

    Hi Kevin,

    Can you share the schematic of your LMKDB1108?

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    Prodigy 20 points

    Michael,

    Here is my schematic.  This took a while to get permission to send this to you so please treat this as confidential. 

    In the schematic, we have the following signals set at the following levels:

    1) REFCLK_PWR_ENABLE -> Driven to 3.3V

    2) CLK_SLEWRATE_FAST -> Pulled to 3.3V

    3) REFCLK_CTRL -> Driven low which should enable CLK0, CLK1, CLK2 and CLK3.   

    4) All the programmable Output Enables are enabled and allow the output clocks.

    5) The CLKIN_P and CLKIN_N clock input is a 100MHz HCSL differential signal that is AC coupled prior to the CLKIN_P and CLKIN_N inputs.  Each leg of the clock is a 700mVp-p SE signal. When I disconnect the 100Mhz clock, both CLKIN_P and CLKIN_N go to about 750mv DC.  

    6) LOS# is pulled up to 3.3V through a 4.75K resistor and then goes directly to a high-impedance cmos input receiver (3.3V logic with 10uA of leakage current).  

  • 0 in reply to Kevin Guy
    Prodigy 20 points

    Michael, again to be clear.  LOS# is always high.  I expect it to be high when the 100Mhz Input clock is on and the clock outputs are valid.  However, LOS# is high when the differential inpuct clock is removed and and the clock inputs float to ~750mv.  I was expecting LOS# to go low when the clock input was removed.    

  • 0 in reply to Kevin Guy
    TI__Genius 9190 points

    Hi Kevin,

    I will get to you tomorrow.

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    Prodigy 20 points

    Michael, have you had a chance to look at this?  I am concerned this part is not working correctly and I should probably switch to a different manufacturer that offers this feature.  Thanks again for your help.

  • 0 in reply to Kevin Guy
    TI__Genius 9190 points

    Hi Kevin,

    Thank you for your patience. I took our EVM into the lab and tried to simulate your issue by holding the CLKIN pins around 750mV. When I did this, the device did not recognize this as a valid input, and the LOS# pin stayed low.

    I have a few questions about your schematic. 

    1. Is there any reason why you are wiring PWRGD/PWRDN low to start? It would allow for a more flexible startup if that were statically wired high.

    2. How are you terminating your input signal (the shunt resistors appear to be DNP'ed)? 

    3. Are you AC or DC coupling your input? You mention that your input pads are held at a bias voltage of ~750mV.

    4. How are you measuring the voltage on LOS#?

    Thanks,

    Michael