LMK04368-EP: Incorrect Clock Frequency Output

It seems to me that this configuration should lock. I do see that the charge pump is set to 1600uA gain as opposed to 3200uA default gain, but this may be appropriate depending on the loop filter used. PLLatinum Sim suggests the default loop filter on the EVM should be stable with 1600uA gain, so unless you modified the loop filter I don't think this is the issue (I'm happy to double-check if you did modify it).

You are providing 300MHz sine wave in on OSCIN. Did you also disable the on-board VCXO? Otherwise there's usually a very loud 122.88MHz interference signal coupled into OSCIN, even when the VCXO is not connected. You can depopulate R73 or FB12 to remove power from the VCXO, which will eliminate any chance of interference.

Hey Derek, 

I depopulated just to be safe and no change. Can you clarify the sequence here; 

On our actual part, we push the following register writes off POR and seem a similar issue. Are we following the proper sequence? 

{0x0000, 0x80}, // RESET=1 (Reset)
{0x0108, 0x0A}, // DCLK2_3_DIV=10 !!UPDATED TO 10
{0x010A, 0x00}, // CLKout2_3_PD=0 (Enabled)
{0x010F, 0x11}, // CLKout3_FMT=1 (LVDS), CLKout2_FMT=1 (LVDS)
{0x0110, 0x0A}, // DCLK4_5_DIV=10 !!UPDATED TO 10
{0x0112, 0x00}, // CLKout4_5_PD=0 (Enabled)
{0x0117, 0x11}, // CLKout5_FMT=1 (LVDS), CLKout4_FMT=1 (LVDS)
{0x0118, 0x0A}, // DCLK6_7_DIV=10 !!UPDATED TO 10
{0x011A, 0x00}, // CLKout6_7_PD=0 (Enabled)
{0x011F, 0x11}, // CLKout7_FMT=1 (LVDS), CLKout6_FMT=1 (LVDS)
{0x0120, 0x0A}, // DCLK8_9_DIV=10 !!UPDATED TO 10
{0x0122, 0x00}, // CLKout8_9_PD=0 (Enabled)
{0x0127, 0x11}, // CLKout3_FMT=1 (LVDS), CLKout2_FMT=1 (LVDS)
{0x0138, 0x21}, // VCO_MUX=1 (VCO 1), OSCout_FMT=1 (LVDS)
{0x013F, 0x23}, // PLL2_NCLK_MUX=1 (Feedback Mux), FB_MUX=1 (CLKOUT8)
{0x0140, 0x8F}, // VCO_LDO_PD=0 (Normal operation), VCO_PD=0 (Normal operation), SYSREF_GBL_PD=1 (Power down), SYSREF_PD=1 (Power down), SYSREF_DDLY_PD=1 (Power down), SYSREF_PLSR_PD=1 (Power down)
{0x0143, 0x11}, // SYNC_EN=0 (Disabled)
{0x0144, 0x1E}, // SYNC_DIS[2,4,6,8]=1
{0x0146, 0x00}, // CLKin1_EN=0 (Not enabled for auto mode), CLKin0_EN=0 (Not enabled for auto mode)
{0x0148, 0x1B}, // CLKin_SEL0_MUX=3 (DAC Locked), CLKin_SEL0_TYPE=3 (Output (push-pull))
{0x0149, 0x33}, // CLKin_SEL1_MUX=6 (SPI Readback), CLKin_SEL1_TYPE=3 (Output (push-pull))
{0x014A, 0x03}, // RESET_MUX=0 (Logic Low), RESET_TYPE=3 (Output (push-pull))
{0x015F, 0x0B}, // PLL1_LD_TYPE=3 (Output (push-pull))
{0x0161, 0x01}, // PLL2_R=1 !!Updated to 1
{0x0162, 0x50}, // OSCin_FREQ=4 (>255 MHz to 500 MHz), PLL2_REF_2X_EN=0 (Doubler Disabled)
{0x0165, 0x32}, // PLL2_N_CAL=50
{0x0173, 0x10}, // PLL2_PRE_PD=0 (Normal Operation), PLL2_PD=0 (Normal Operation)
{0x0168, 0x01}, // PLL2_N=1
{0x0169, 0x50}, // PLL2_CP_GAIN=2 (1600 uA)
{0x016E, 0x13}, // PLL2_LD_MUX=2 (PLL2 DLD), PLL2_LD_TYPE=3 (Output (push-pull))
{0x0555, 0x00} // SPI_LOCK=0 (Registers unlocked)
};

The write to PLL2_N (0x168) should happen after the write to PLL2_CP_GAIN (0x169), since calibrating the PLL while the charge pump gain is changing can produce strange results. I am in the process of pushing for the programming sequence instructions to be clarified to indicate that 0x168 should be written after everything else, to trigger the VCO calibration once the power stabilizes in all the internal LDOs and once the loop-affecting registers have settled. I'd also suggest inserting a pause between the PLL2_N write and the other writes to allow for that settling time, or else write 0x168 again after a few milliseconds and see if that puts it in lock.

PLL2_N_CAL = 50 (0x165 = 0x32) should be PLL2_N_CAL = 5 (0x165 = 0x05), presuming PLL2_P is left at the default value of 2.

You should probably set PLL2_WND_SIZE = 1 (0x169 = 0x30 instead of 0x50) since the phase detector is operating above 240MHz.

You might want to set SPI_3WIRE_DIS = 1 (0x0 = 0x90) if your SPI bus can't handle LMK04368-EP attempting to drive SDIO as an open-drain line during readback. 3-wire and 4-wire readback can happen simultaneously. Of course, this only matters if you attempt to read back from the LMK04368-EP.

The rest looks accurate to me...

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If those cleanup items don't help, the next thing I'd check is whether the R and N ports are actually seeing the expected signals at the expected frequencies. You can configure PLL1_LD_MUX and PLL2_LD_MUX to output a divide-by-4 of the input to the R port and the N port at the phase detector, which can be probed to ensure the clocks into the phase detector are doing what you expect. This can sometimes help identify nonmonotonicity issues if you have a strange/astable R/N signal.

What is the amplitude of the 300MHz sine wave? Is it being properly terminated? The VCXO signal normally on OSCIN is too large amplitude for the OSCIN port, so there is a resistive attenuator to reduce the amplitude - if this resistive attenuator (the 100Ω R61) has a path through the AC-coupling capacitor to the OSCIN network, and you're providing 300MHz on OSCIN_N, this might be affecting signal integrity or amplitude even with the VCXO disabled.

AFAIK the signal is terminated properly. This is just a ~-10dBm sine at that frequency. 

I did attempt to clean up the registers to seemingly no effect

-10dBm might be too low for the OSCIN input receiver - I believe that's about 200mVpp, which is just barely at the minimum of our input signal swing requirements. Does it lock with a 0dBm signal?

No, not getting any lock on the board and I still get this ~307MHz output regardless of whether something is on the OSCin or not. 

Nothing else is jumping out at me. I'm going to try to replicate your setup on an EVM and get it to lock - I'm currently away from the lab but I'll be back in tomorrow. Apologies for the delay.

Thanks! I found an alternate config that is giving me lock but will make a note in case we need to do more troubleshooting. Thanks for the help!