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CDC6C: BAW oscillator use for AM6442

Shuji Ishiwata
Mastermind 8880 points

Part Number: CDC6C
Other Parts Discussed in Thread: AM6442, , LMK6C

Tool/software:

Hi All,

I would like to use a BAW oscillator as the oscillation source for the AM6442.
Is the CDC6CE025000ADLER suitable?

Best Regards,
Ishiwata

  • 0
    TI__Genius 16920 points

    Hi Ishiwata, 

    This thread was assigned to the clock and timing group, I'll redirect it to the Sitara product line to answer your question about using CDC6C as the clock source for the AM6442. 

    Regards, 

    Connor 

  • 0 in reply to Connor Lewis
    TI__Guru 64655 points

    Are you planning to use the SerDes inside the AM64x device to implement USB SuperSpeed or PCIe?

    Regards,
    Paul

  • 0 in reply to peaves
    Mastermind 8880 points

    Hi Paul,

    Thank you for your reply.
    I haven't yet confirmed the specifications for using AM64x.
    The customer is considering SiTime's SiT8008B. I wanted to suggest a TI product.
    I asked if I could use a BAW product for that purpose.

    I think it will be necessary when proposing BAW products, so can you give us some background on implementing USB SuperSpeed ​​or PCIe?

    Best Regards,
    Ishiwata

  • 0 in reply to Shuji Ishiwata
    TI__Guru 64655 points

    The TI clock/oscillator team wanted to be sure their BAW oscillator would work with the TI Sitara processors. They took one of our AM64x EVMs which previously passed all of the USB SuperSpeed and PCIe compliance tests with its original reference clock source and measured the PLL jitter performance before replacing its original clock source with a TI LMK6C device. They found the PLL jitter performance improved with the TI LMK6C source. This indicated the TI BAW oscillator provided a more than acceptable reference clock for AM64x.

    I'm not familiar with the device you mentioned, so the customer needs to confirm the TI clock source they select meets the requirements which we plan to publish in the next revision of the AM64x datasheet. The non-SerDes use case requirements have already been added to the datasheets of several newer devices. You can reference the AM62Ax, AM62Dx, or AM62Px datasheets to see these requirements, which are the same as the AM64x non-SerDes use case requirements.

    The AM64x datasheet will have an additional Phase Noise parameter that must be applied if they are planning to use the AM64x SerDes to implement USB SuperSpeed or PCIe operating without a common external clock source.

    The maximum phase noise profile should less than:
    -92.3 dBc/Hz at 100Hz
    -122.3 dBc/Hz at 1kHz
    -132.3 dBc/Hz at 10kHz
    -142.3 dBc/Hz at 100kHz
    -152.3 dBc/Hz at 1MHz

    The Phase Noise parameter is only applicable when the SerDes PHY is used for USB SuperSpeed, or PCIe operating without a common external clock source.

    Regards,
    Paul

  • 0 in reply to peaves
    Mastermind 8880 points

    Hi Paul,


    Sorry for the late reply.

    Thank you for your reply.

    I will confirm with the customer whether they plan to implement USB SuperSpeed ​​or PCIe.


    In your comment
    " They took one of our AM64x EVMs which previously passed all of the USB SuperSpeed and PCIe compliance tests with its original
      reference clock source and measured the PLL jitter performance before replacing its original clock source with a TI LMK6C device.
      They found the PLL jitter performance improved with the TI LMK6C source. This indicated the TI BAW oscillator provided a more than
      acceptable reference clock for AM64x.
    "
    Do you have any evaluation results for this?

    Best Regards,
    Ishiwata

  • 0 in reply to Shuji Ishiwata
    TI__Guru 64655 points

    We do not have any official report which we plan to share with customers. We are only willing to say that our EVM was able to pass the USB Superspeed and PCIe compliance tests with the original EVM clock source as well as the TI LMK6C clock source.