LMX2694EPEVM: Design method for LMX2694EPEVM

Thanks for the reply Noel Fung

Thanks for the explanation about T3/T1 and Gamma parameters.

By actually swinging the parameters and verifying the sim results, I now understand the nuances of what you are saying.

I also now understand the difference between the constants. So it was a matter of market availability.

I now understand that with a similar setup, I can get the same results as in Figure 6.

Let me ask a follow-up question.

I am currently looking to run this evaluation board at 8 GHz and 8.001 GHz.
(I would like to run this PLL in Fractional mode.)
The parameter that I want to optimize with the highest priority is SNR. Can I find the optimal C/N by using the following Sim settings? I would appreciate any suggestions for improvement.
I would like to determine the constants of the Loop Filter based on the results obtained from this sim.

Also, when performing optimization here, could you please tell me whether it is better to uncheck the Auto checkbox in the red box below or to check the Auto checkbox?

Please answer the above questions.

Hi Noel Fung.

I have an additional question, which I would like to ask you to answer together with the above question.

I have found the Loop Filter at 8001GHz using PLLatinum.
The constants are shown in the image below.

When I changed the constants on the evaluation board to be the same as the sim result based on this result, the phase noise was different from the sim result as shown in the image below.

I would like to know the cause of this difference.

Hi Naohiro-san,

We have a PLL Sim training video in below link.

https://www.ti.com/video/6330930382112?keyMatch=pllatinum%20sim&tisearch=universal_search

Better SNR means lower phase noise or jitter. Usually a wider loop bandwidth + higher phase margin can return lower jitter. 

We can manually type the four target parameters and click the Calculate Loop Filter button to get the suggested values and actual loop performance.

We can uncheck the boxes and move the slide bar to quickly see the effect.

We can also provide a target jitter to the tool, it will come up with the best possible configuration for us.

The video has the details.

Your plot shown the loop bandwidth is just 50kHz with a small phase margin. Likely this is due to wrong component values are populated.

Hi Noel Fung.

Thank you for your reply.

I understood that the jitter parameter is the most effective for SNR.

Based on the results of the training video, I further increased the phase margin and loop bandwidth from 50kHz to 206kHz.
In order to achieve good SNR, we designed the system as shown in the following image.
The jitter parameter of Filter Otimizer is set to 30.
Loop Bandwidth, Phase Margin, Gamma, and T3/T1 Ratio were set to Auto
- MASH Seeds was set to Optimize Seeds for Spur Jitter and the calculation was performed
As a result, SNR of -49.5 dBc/Hz was obtained.

The simulation results did not show any spurious signal, but the actual measurement results showed a 1 MHz spurious signal.

(1)Please tell me the cause of this 1MHz spurious.

In addition, I obtained a result of -49.5dBc/Hz for SNR with Sim, but it was -27.34dBc/Hz in the actual measurement.

(2)Please tell me the cause of the difference between the Sim and measured results.

Based on the Sim results, we changed the parameters of the evaluation board as follows.
The following are the part names of the evaluation board and the changed parameters.
C1LF: 0.47nF -> 0.12nF
C2LF: 68nF -> No change
C3LF: 1.8nF -> 2.2nF
R2LF: 0.068kΩ -> 0.082kΩ
R4LF: 0.018kΩ -> 0.027kΩ

Please reply to questions (1) and (2).
Also,Please answer the above questions.

Hi Naohiro,

The sim already told you there are spurs:

With 100MHz input and 8001MHz output, for sure there will be Integer Boundary Spurs (IBS) at 1MHz. Fractional spurs is also 1MHz. Sub-fractional spurs appear at 1/2, 3/2 of fractional spurs frequency. 

The sim can predict the spurs frequency but not able to accurately predict the spurs level as this is very much depends on the chip layout. The spurs level also depends on the input clock format and level. 

You may read LMX2582 datasheet, section 8.1, for details of spurs.

Your measurement integrated all the noise between 100Hz and 100MHz, including the spurs, so the jitter and SNR is bad. If you omit spurs in your measurement, you should get SNR close to simulation. 

To reduce this spurs, use smaller charge pump current, use square wave input clock, use a weird PLL NUM such as 10000001.

Hi Noel Fung.

Thanks for the reference on the factors of spurious components.

To reduce this spurious component, I am currently thinking of using a clock buffer to input differential input signals.

(1) Is it possible to input LVPECL signal format?
Is it possible to input LVPECL signals or only LVDS?

(2) Is it possible to input differential signals directly to the factory evaluation board? Is there anything we need to change on our end?

Please answer the above two questions.

Hi Noel Fung.

By using LVPECL as input, the integrated C/N value has improved.

Thank you very much.

Question 1) Please tell me why spurious improves with differential signal input.

Question 2) In TI PLLatinum, when I try to analyze up to kHzOrder like 7689.33MHz, my PC gets stuck. Please tell me a simple method to derive an approximate value.

Please answer the above two questions.

Hi Noel Fung.

I understood that differential signals tend to be better for spurious, and that the clear mechanism is complex and not obvious.

I have a question about Sim and actual measurement in 0.1 MHz increments.

Sim and actual measurements were made at 7999.9MHz~8001.1MHz. The measurement results are as follows.

The signal used for the measurement was the LVPECL signal.

The following are the measurement results at CP15mA.

The following are the measurement results at CP3mA.

Ideally, we would like to achieve -46dBc/Hz or less.

Can this result be any better?