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LMK04616: Locking time drift at low temperature (-30°C)

guillaume lusson
Prodigy 10 points

Part Number: LMK04616

Tool/software:

Hello,

We are using Clock Jitter Cleaner LMK04616ZCR component on our design in production.

We have observed a drift of the locking time vs temperature

As shown in the graph here below, we have measured the locking time at several temperatures from +20°C going down to -30°C, and to -38°C for 1 case.

The different curves correspond to different configuration on our design. The LMK configuration remains the same for all those curves.

We plan to have a final design operating from -40°C. By extrapolating those curves, it is expected to get a locking time of about 70ms. Which is much higher than the 10ms measured at ambient temperature (+20°C).

What would be the root cause for that different locking time between -30°C (-40°C) and + 20°C?

Are our measures coherent from you point of view?

The measures have been done on two different devices (with different date codes : 29AZQ5W and 25AJ4VW). what level (percentage) of dispersion shall we expect on the locking time at -30°C and -40°C?

Thank you for your feedbacks,

Best regards,

Guillaume LUSSON

  • 0
    TI__Mastermind 19771 points

    Hi Guillaume, 

    I will forward this question to our designers to see what they say.

    It is not surprising that the lock time is impacted by a change in ambient temperature, but I am not sure that we have characterized the change in lock time over temperature. What has been characterized is the temperature drift that can be tolerated while maintaining continuous lock - that value is 145 deg C. 

    That being said, a difference of 60 ms (is it ms or us? The graph you shared says us) seems significant for a temperature difference of 50-60 deg C - and it likely seems the result of significant cycle slipping.

    Thanks,

    Michael

  • 0
    Prodigy 10 points

    Hello Mickaël,

    Thank you for your feedback.

    On the graph, it is µs (I'm sorry, I could not get it clearer when I attached it to the post).

    The curves at -30°C cross the 50 000µs line, so 50 ms.

    What do you mean by 'cycle slipping'? 

    Best regards,

    Guillaume

  • 0 in reply to guillaume lusson
    TI__Mastermind 19771 points

    Hi Guillame,

    The phase detector of the PLL has to track towards the appropriate phase offset in order to achieve lock. It does this by sending positive or negative charge pulses to the VCXO/VCO in order to steer the phase appropriately. 

    What can happen (due to a large spike in noise, or due to the pulses not being as strong, like what may occur when operating at low temperatures) is that the phase detector can find a stable frequency whose phase is actually a cycle ahead or behind, resulting in the phase detector taking longer to reach the appropriate phase.

    Thanks,

    Michael