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LMK04826: PLL1 cannot be locked

xu lang
Prodigy 10 points
Part Number: LMK04826


Tool/software:

This is my configuration. The goal is to use LMK04826 to eliminate jitter. After power supply, LMK04826 cannot lock, and the output frequency is around 99.9997MHz. May I ask what problems need to be investigated

  • 0
    TI__Mastermind 34240 points

    Two things immediately stand out to me:

    1. 10MHz input on LMK04826 may not meet the minimum slew rate requirements, especially if 10MHz is a sine wave input. The minimum input slew rate is 0.15V/ns, whereas a 10MHz sine wave can only achieve 2π * 10MHz * Vpk = about 0.1V/ns with a 3.3Vpp input. Ensure that the minimum input slew rate is satisfied before proceeding.
    2. I see in PLLatinum Sim that Kvco has been set to 25Hz/V. This is a very narrow tuning range. Are you using a tunable OCXO or TCXO as the PLL1 VCO? Is it possible that the PPM error between the reference and the VCO is sufficient to prevent lock across the tuning range? You can measure the voltage at the CPout1 pin, and depending on whether it is saturated at the rails, and if so to which rail, this may tell you something useful about the problem.

    A few other possibilities that I think are less likely:

    • Is the charge pump polarity correct for the tuning slope of the VCO? Normally positive is correct, but it's quick to double-check.
    • Is OSCout interfering with OSCin? Particularly for LVCMOS with unterminated loads, victimizing a single-ended OSCin, there may be some noise coupling from OSCout onto the unused OSCin pin. You could try powering down OSCout and see if this makes a difference.
    • Is this being tested on an EVM? If so, have you removed power to the on-board 122.88MHz VCXO? This could also be injecting crosstalk onto the OSCin traces.