Part Number: TPL5100
Tool/software:
Hi !
I'm designing a new timer function using TPL5100.
As far as I know the timer will toggle the DRV signal after each elasped delay time as long as PGOOD is high right ?
The DONE signal is connected to GND and TCAL is N/C
My design will use PGOOD as a start trigger for the counter and then when DRV signal toggles it will clock the D-type flip-flop to catch the first delay event, se schematic below
Questtion, the DRV output is normally used to control a MOSFET gate, but can it sink and source a SN74LVC1G74DCTR clock input in safe manner, need of a weak pullup maybe ?
Kind Regards,
Ola
