LMK1D1204: clock output issue

Nandini Muralidharan

Intellectual 820 points

Part Number: LMK1D1204

Tool/software:

Hi,

I am using LMK1D1204 IC in my design as below

SG3225's output clock is measured and seems to be ok.

But output clock of the LMK buffer seems to be non-monotonic and looks worser with diff probe as well.

Measurement with Single ended probe on 'P' and Ground clip connected to board ground

Measurement with diff probe between 'P' and 'N'

Can you pls tell me what can be done to tune them?

The clock outputs from LMK buffer go to Virtex Ultrascale+ FPGA where we use DIFF_SSTL12 Standard.

over 1 year ago

0 vicente flores prado over 1 year ago

TI__Mastermind 32152 points

Hello Nandini,
Is the 100Ohm differential termination on the output side near the Rx?

Best regards,

Vicente

0 Nandini Muralidharan over 1 year ago in reply to vicente flores prado

Intellectual 820 points

Hi Vincente,

We have on-board 100-ohm resistor at the RX (FPGA) end.

Thanks

0 vicente flores prado over 1 year ago in reply to Nandini Muralidharan

TI__Mastermind 32152 points

Hi Nandini,
This makes more sense.
But what is the purpose of the bias network?
If I understand correctly this is setting the bias to 0.6V at each pin?

Normally we have the differential termination before the AC coupling caps as well.

Have you done any SI simulations using IBIS model?

Best regards,

Vicente

0 Nandini Muralidharan over 1 year ago in reply to vicente flores prado

Intellectual 820 points

Hi Vincente,

Yes, The bias network sets 0.6V at each pin. Since the FPGA bank voltage is 1.2V powered, we don't have IOSTDs like LVDS available on it.

Are you saying there is an internal diff term in the LMK buffer as well?

We did do an SI simulation and the result is as below.. we are using the same SSTL12 settings.

0 vicente flores prado over 1 year ago in reply to Nandini Muralidharan

TI__Mastermind 32152 points

Nandini,
Where are you probing on your board?
Is this at the receiver end?
Is the GND reference close by?

LMK1D does not have internal differential termination.
What I'm saying is that the differential termination is before you AC couple the signal.

Best regards,

Vicente

0 Nandini Muralidharan over 1 year ago in reply to vicente flores prado

Intellectual 820 points

Hi Vincente,

I have shared two images. In case of Single ended probe, the ground is nearby. In case of diff probe image that was shared, one the of the probe tip is kept at P and another end at N of the same pair. My concern is on this diff pair waveform

Also I am probing at the output pin of the capacitor using the diff probe.

Regards,

Nandini

0 vicente flores prado over 1 year ago in reply to Nandini Muralidharan

TI__Mastermind 32152 points

Understood.
Can you please probe at the pins of the receiver?

How far along the transmission line do the AC coupling caps reside?

Best regards,

Vicente

0 Nandini Muralidharan over 1 year ago in reply to vicente flores prado

Intellectual 820 points

Hi Vincente,

Probing at the resistor (near the FPGA) helped. The waveform looks better now.

Above is the waveform captured with DIFF probe. Since Vpk-pk is 665mV, can we say differential voltage (Vdiff) is 665/2 = 332.5mV?

Also, based on the single ended probe measurement shared before if we consider Vmax as 750mV, can we say common mode voltage= vmax-(Vdiff/2) = 750 - (332.5/2) = 583.75mV?

If not, pls share how to find the common mode voltage from these waveforms.

Thank you

Nandini

0 vicente flores prado over 1 year ago in reply to Nandini Muralidharan

TI__Mastermind 32152 points

Hi Nandini,
Yes, we always want to probe near the Rx, never in the middle of the T-LINE or you can end up seeing weird reflections like you did previously.
Now, you won't be able to calculate the VCM of this signal if this measurement is done post AC coupling cap.
The AC coupling cap is blocking the DC offset.
You will need to probe before the coupling cap to see where VOH/VOL reside and from there the VCM is (VOH + VOL) / 2

Best regards,

Vicente

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LMK1D1204: clock output issue