Other Parts Discussed in Thread: LMX2615-SP
Tool/software:
I am using a oven controlled oscillator at 100Mhz frequency with a calculated worst case jitter of 1.9e-12 seconds. I input this into oscinp and oscinn as a differential signal, and pass it through to oscoutp/oscoutn as a buffered signal that is then used as the reference clock for LMX2615-SP. We also use the distribution mode in the LMK with a feedback clock coming from the LMX that is 2.5Ghz, and is used to create (2) 31.25Mhz (sysref) and a 250Mhz clock (sysref) on clock outputs 0, 1, and 2.
Im trying to understand what contribution the LMK has in terms of phase noise/additive jitter for a worst case scenario in this clock tree. I find i n the LMK datasheet that the LVDS output has a 50 fs additive jitter for 245.76 MHz Output Frequency, 12k-20MHz integration bandwidth. Can I use this, or should I use TICS pro or PLL Sim to generate a phase noise plot?
