Tool/software:
I can't seem to find a combination of register settings that will keep the outputs muted until APLL/DPLL lock to PRIREF. Either the outputs are muted all the time or they're never muted.
I'm using the TICSPro Advanced page to try and set the flags but there's some ambiguity in the register descriptions. For instance, MUTE_DPLL_PHLOCK says "DPLL mute enabled during phase lock" but does that really mean "mute while the DPLL is locked" (which doesn't make any sense to me) or "mute while the DPLL is trying to acquire a lock"?
Anyway, I've attached my tcs file which is pretty basic... 1MHz in to PRIREF, 12.8MHz TXCO in to XO and 10MHz out to OUT3 in CMIS(+/-) mode. A lock to PRIREF takes about 3-5 seconds and I'm trying to mute the output until that lock. All the sync options are unchecked because it's the only config I can get to work.
Some guidance would be appreciated.
Thanks!
