• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 22 subscribers
  • Views 926 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CDCE62005 strange behavior

Janos Lazanyi
Prodigy 20 points

Other Parts Discussed in Thread: CDCE62005

We have built a PCB using the CDCE62005 and facing three problems.

The usage scenario is rather simple. There are two clock sources, both 40 MHz. The primary section is connected to a connector, and the secondary side is driven by a local oscillator. If there is no primary input, the CDCE62005 planned to switch to the “backup” secondary (oscillator input). All outputs are used, some of those in LVDS some in CMOS mode.

 We have designed a CDCE62005 firmware download tool that reads the output file of the CDCE62005 GUI, makes programming, EEPROM refresh (if needed), calibrates and check for lock status.

 We have 3 problems:

 1, At a first stage of the bring up, we have faced the following problem. (The chip is running fixed from onboard oscillator, CMOS input used). Everything is fine all frequencies (25, 64, 96 MHz) are good, lock is ok, BUT on the output 0 there is no clock !!! Used in LVDS mode. All the other outputs are working fine, we can output the same frequency to other outputs, but 0 is not working …. (This problem was temporary solved with a bypass wire.)

We have checked the issue on multiple PCBs !?

 2, At the final application the clock input standard will be LVDS.  So we have reconfigured the secondary input to LVDS. (oscillator + LVDS driver DS90LV011). We do not get lock ! And if we configure one output to be directly connected to the input, nothing is there. We tried many configuration, and found out that turning “Fail safe” off, solves the issue …We tried all combination of internal/external  AC/DC. None is working, while the failsafe is on.

OK. We can live with this somehow.

 

3, BUT! We can not get the primary input into lock in LVDS mode. The CMOS mode is ok. LVDS  AC/DC/Failsafe on/off is not locking in any combination, though direct routing to the primary input to one of the output is ok. I think the smart mux can not detect the valid source, that is why it is not enabling the PLL at all, or something like this…. (It is crazy because the same source connected to the secondary input works really nince, when failsafe is off!!!! )

 

Do you have any idea???

 

PCB is ok I think, we have good decoupling + supply filtering and dedicated LDO for the CDCE62005.

  • 0
    TI__Guru* 81035 points

    Hi Janos,

    I am sorry for the issues you are facing. Can you send me the register settings you are using so we can verify the settings in our lab? Also, we can double-check the schematic for potential issues if you are able to share it.

    Thanks and best regards,

    Matt

  • 0
    TI__Expert 4150 points

    Hi Janos,

    if you are uncomfortable to post your settings to E2E, feel free to send an email to cdce62005_inquiry@list.ti.com and it will get directly to the application support team for the CDE62005.

    Best regards, Falk Alicke

  • 0
    TI__Expert 4150 points

    Hi Janos,

    thank you for sending your schematic and ini file offline. Your ini-file was completely corrupted. It needs to show the register numbers from zero to eight as the last digit. For some reasons, yours were all "F". Here is the code for a new ini file. Input frequency would be 40MHz.

    REGISTERS
    0 eb2c0320
    1 eb120321
    2 eb0a0302
    3 eb400003
    4 eb400004
    5 10100ab5
    6 945e1af6
    7 3da1fbf7
    8 40009cf8

    Attached you find the full ini-file.

    http://e2e.ti.com/cfs-file.ashx/__key/CommunityServer-Discussions-Components-Files/48/5224.pll_5F00_test_5F00_suggestion_5F00_TI.ini

    Another thing we observed is the choice of internal loop filter components. Please try the following instead:

    CP current = 750uA
    C1=16.5pF
    R2=9.0k
    C2=473.5pF
    R3=5k
    C3=19.5pF
    --> Phase margin is 60degree, LPW=246kHz, gamma ~2.4
     
    The reason we didn't like your initial selection was the very large R2 and the particular small C1. The larger you set R2 and the smaller you set C1, the more susceptible the loop will be to parasitics and charge pump current artifacts (missmatch, noise, switching behavior), which may impact loop stability.
    For example, if C1 is selected C1=1.5pF, and the actual device is off by a couple of pF, the phase margin might change dramatically. Also, with a PFD frequency of 8MHz you had initially choosen a loop bandwidth of over 800kHz. You want at least a 10x lower loop bandwidth than PFD frequency and practically you want it even lower in order to reduce spurs (DJ). Thus, the above new loop filter settings will get you a much more stable setting.
     
    Hope this helps! Best regards. Falk Alicke

    PS: here a screeshot of the GUI that was tested successfully in the lab with the ini file in this email:

     

  • 0 in reply to Fritz
    Prodigy 20 points

    Hello Fritz,

     

    We could have known this a bit earlier.... There were so many sytomes of mailfunction....

    The problem was during the SPI programming of the chip. Our FPGA programmed somehow wrong of the chip select line, and only some part of the config were transfered into the chip. .The funny thing is that the output frequency and PLL config was good, so we thought the SPI is ok.

     

    Many thanks for your support !

  • 0 in reply to Janos Lazanyi
    TI__Expert 4150 points

    Hi Janos, you are welcome. We are glad this worked out for you! Best regards. Falk