LMK05318B: configuration for best jitter performance

Hi Alberto,

1. Is it possible to achieve a jitter < 70 fs using only APLL1 and turning off DPLL?
   1. [JB] Yes.The performance is 47 fs for 250 MHz across 12 kHz to 20 MHz offsets. Here I use SMB100A set to 50 MHz as the XO input with the DPLL disabled.
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2. What is the disadvantage of not using DPLL?
   1. [JB] The DPLL allows for the use of the following features: DCO operation, holdover, hitless switching, and flexible input lock to more than one input, 1PPS input lock.
3. Can I use a 50 or 100 MHz XO in the case where DPLL is turned off? (The ratio between the input and output frequency of APLL1 would be an integer.)
   1. [JB] Yes, the above plot uses integer-N divider mode to use the 50 MHz XO input.
      
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   4. e2e_XO=50M_OUT=250M_integer mode.tcs
4. What happens if I use DPLL but without the reference (PRIREF or SECREF)? Is this an allowed configuration?
   1. [JB] Yes it is allowed, however, keep in mind you can save power when the DPLL is disabled. You still don't want to use the DPLL with 50 MHz or integer related XO inputs because that can cause integer boundary spurs when the DPLL is used (because the DPLL must operate in fractional-N divider mode).
5. Can I use a 25 MHz clock from an FPGA as PRIREF for DPLL?
   1. [JB] Yes, however, make sure to use a non-integer related XO input such as 48 MHz, 54 MHz, 38.88 MHz, 24 MHz...etc.

Regards,

Jennifer

Hi Alberto,

You are correct, below the APLL LBW (1 kHz for LMK05318B using the default APLL loop filter settings), the XO input phase noise dominates the output phase noise.

If the XO input is noisy below 1 kHz, then we will se such impact on the outputs below 1 kHz.

My app note helps illustrate this better, see the section on Phase Noise Profile:

https://www.ti.com/lit/an/snaa396a/snaa396a.pdf?

For APLL only operation, the XO input domiantes below APLL LBW.

For APLL + DPLL operation, the XO input and REF input dominate below the APLL LBW.

Yes, LMK05318B is the recommended part because APLL1 can be used which has the ultra low jitter BAW VCO. We also have the 4 output version, LMK5B12204, and is part of the same family.

Between the previous config (APLL only) and this new config (DPLL locked to 25 MHz with a 48 MHz XO input), the power saving is 30 mA. All outputs are enabled.

e2e_XO=48M_REF=25M_OUT=250M.tcs

Regards,

Jennifer

Hi Alberto,

The important thing is to meet the datasheet XO input requirements, specifically the input frequency, voltage swing, and slew rate.

If such requirements can be met, then your clipped sine wave input is OK to use.

Regards,

Jennifer