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CDCLVC1104: Recommended part number of crystal oscillator

ttd
Mastermind 9385 points

Part Number: CDCLVC1104
Other Parts Discussed in Thread: LMK6C, LMK1C1104,

Tool/software:

Dear Technical Support Team,

Do you have recommended part number of crystal oscillator )? LVCMOS 100MHz.

The datasheet said “input slew rate” is 1(min) and 4(max)  V/ns.

I have been lookin into this crystal oscillator, but I couldn't find it currently

Best Regards,

ttd

  • 0
    TI__Mastermind 32152 points

    Hello ttd, 
    Any square wave XO should be able to hit that input slew rate spec. 

    Take LMK6C for example where the output slew rate minimum is 2V/ns. 
    I would just recommend to to find a low jitter XO with a square wave output. 

    Best regards, 

    Vicente 

  • 0 in reply to vicente flores prado
    Mastermind 9385 points

    Hi Vicente,

    Thank you for your support.

    LMK6C  output slew rate minimum is 2V/ns and maximum 12V/ns for HCSL.

    LVCMOS doesn't have this oupput slew rate and tr/tf are only typ and  max(no min spec).

    Could you look into other parts number to be satisfied with slew rate? 

    I couldn't find LVCMOS XO(min / max spec for slew rate or tr/tf) such as Si Time.

    MHz Oscillators - SiTime

    Best Regards,

    ttd 

  • 0 in reply to ttd
    TI__Mastermind 18361 points

    Hi ttd,

    I am not sure why you are looking at the HCSL specs if you are planning to use an LVCMOS buffer. There is no specified maximum output slew rate for LVCMOS for the LMK6C, but the datasheet does specify a typical rise time for 20-80% of VOH-VOL. To determine a maximum slew rate, one can simply subtract VOL from VOH (for 3.3V case, this is 1.98V), multiply that by 0.6 (1.118V), and then divide that by the typical rise time (1.188V / 0.5 ns = 2.376 V/ns). This value satisfies the constraints of the CDCLVC1104, but my suggestion would actually be to use the LMK1C1104 with the LMK6C. The LMK1C1104 is a LVCMOS buffer with a wider tolerance range for input slew rate (it only specifies a minimum input slew rate of 0.1 V/ns). It has better jitter performance and it p2p with the CDCLVC1104.

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    Mastermind 9385 points

    Hi Michael,

    Thank you for your advice.

    I got how do I calculate slew rate with VOH,VOL and typical rise time.

    Q1

    Do you have  minimum rise and fall time for LMK6C?

    I already adopted CDCLVC1104 on my board, so I'd like to estimate worst case.

    I understood that LMK1C1104 is best. 

    Q2
    What is the purpose (especially the slew rate) for which CDCLVC1104  was released?
    I'm wondering if the slew rate was specified in order to maintain the accuracy of the noise floor and jitter specs as a result of the characterization.

    Q3
    Also CDCLVC1104, what are each risks associated with the input of clocks when the slew rate is faster or slower than the specs?

    Best Regards,

    ttd

  • 0 in reply to ttd
    TI__Mastermind 18361 points

    Hi ttd,

    See the image below from the datasheet specifying rise/fall time for varying load capacitance values for the LMK6C. 

    A maximum rise/fall time of 1 ns is specified, but there is no such specification for the minimum rise/fall time.

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    Mastermind 9385 points

    I understood that since there is no temperature drift in rise/fall time, there is no min stipulation either. Therefore, if I estimate the slew rate at 2.376 V/ns in typ, it will be within the range of min=1V/ns /max 4V/ns of the input slewrate of CDCLVC1104, so is my understanding correct?

    Also, please answer Q2 and Q3.

    Q2
    What is the purpose (especially the slew rate) for which CDCLVC1104  was released?
    I'm wondering if the slew rate was specified in order to maintain the accuracy of the noise floor and jitter specs as a result of the characterization.

    Q3
    Also CDCLVC1104, what are each risks associated with the input of clocks when the slew rate is faster or slower than the specs?

  • 0 in reply to ttd
    TI__Mastermind 18361 points

    Hi ttd,

    ttd said:
    if I estimate the slew rate at 2.376 V/ns in typ, it will be within the range of min=1V/ns /max 4V/ns of the input slewrate of CDCLVC1104

    This understanding is correct.

    ttd said:
    Q2
    What is the purpose (especially the slew rate) for which CDCLVC1104  was released?
    I'm wondering if the slew rate was specified in order to maintain the accuracy of the noise floor and jitter specs as a result of the characterization.

    The input slew rate is specified for the purpose of phase noise performance. If the minimum spec for the input slew rate is not satisfied then the buffer will present significant phase noise degradation. 

    ttd said:
    Q3
    Also CDCLVC1104, what are each risks associated with the input of clocks when the slew rate is faster or slower than the specs?

    If the slew rate is slower than the spec, then the risk is greater phase noise. If the slew rate is faster than the spec, then the risks are significantly less significant, so long as the swing/input levels are within the absolute operating specification - if that were to happen, then that would run the risk of damaging the device.

    Thanks,

    Michael