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CDCUN1208LP: Clock buffers with automatic crossover

Part Number: CDCUN1208LP

Tool/software:

Just curious if you could point me to any other parts you may offer with the smart input multiplexer or similar feature used in your CDCUN1208P.

Ideally we are looking for LVDS or LVCMOS.  We have 4x redundant signals that we are trying to select between so either 1x, 2x, or 4x channels per package would work that mux 2 input signals to 1 output signal..  Appreciate any information you may have.

  • Hello Craig, 
    We have LMK1D210x family if you require a 2:2 MUX. 
    LMK1D120x family are buffers with selectable input input with 1:n copies, n being the output count. 
    LMK1D family are LVDS outputs. 

    Best regards, 

    Vicent e

  • Sorry didn't make the original question clear.  We're looking for an IC that can automatically switch between 2 inputs so either a single dual or quad 2:1 mux that has automatic switching from a primary path to a secondary path if the primary path clock disappears.  This is similar to what is used for the CDCUN1208P referenced above but is more outputs than what we need.  Was hoping to just see what other ICs might have this automatic switching behavior for a 2:1 mux.

  • Gotcha. 
    Okay sounds like you're looking for a device capable of hitless switching. 

    From my understanding, no standard clock buffer can do this. 
    Typically, hitless switching requires a PLL for this kind of switchover to be able to occur. 

    No analog clock buffer on the market has this feature. Well at least not that I'm aware of. 
    The best you will find is most likely two redundant inputs controlled via an input selection MUX with many devices having LOS (loss of signal) detection. 

    If LOS is triggered, you will need to manually (either by pin strapping or software) change the state of the input selection input to changes between ref clks. 

    Now what you can do is use a DPLL (network synchronizer) and have the four redundant inputs and have the outputs generated be identical to the input clock. 
    Utilizing the internal PLLs, we can hitless switching occur in case one of the redundant inputs is lost. 

    For the DPLL to be able to operate, it requires an extra XO for the APLL to be able to provide output clock when the reference is lost. 

    I think one of our DPLLs can work here, what is the clock frequency in question here? 

    Best regards, 

    Vicente 

  • Thanks Vicente, the only part that i have really seen that appears to have something like it is the CDCUN1208LP that i referenced above.  Just thought there might be other parts TI offers that does a similar thing. 

     

  • Hi Craig, 
    I see what you mean. I apologize for having not understood in the first place. 
    Unfortunately, nothing with this level of functionality for four redundant inputs unfortunately. 

    Best regards, 

    Vicente 

  • No problem Vicente. 

    i have 4 different signals that i'm trying to do a 2:1 select on so that i can have some redundancy if one of the signals drops out.  The chip above would work for our application but i would need 4x of them and i would only need 2 of the 8 outputs so it's overkill for what i need.  For each of the 4 signals it would look something like the following which would be replicated 4 times:

    2 clks in => 1 clk selected and does some internal work on a PCB => pass through a 1:2 fanout to the next board.

    Basically trying to eliminate single point failures from destroying the signaling of the whole bus.

  • Hello Craig, 
    Understood. 
    We do not have one IC capable of doing this across 4 different input signals. 

    CDCUN1208 or a DPLL are your only viable options. 

    Best regards, 

    Vicente