LMK5C33216A: Difficulties getting the analog delay of SYSREF output to work

Christoph,

Our expert for this device is currently out of office, and will return tomorrow. Please expect a response by then.

Thanks,

Kadeem

Hi Christoph,

I will need more time to look at this. I will reach back early next week with a response.

Regards,

Jennifer

Hi Jennifer,

Thanks for having a look at this. Looking forward to your insights!

Regards,

Christoph

Hi Christoph,

I observe similarly with output going away with SYSREF + ADLY. Let me look more into this and discuss with my team if this is expected.

Can you please clarify why you need to use the SYSREF with analog delay? Also,how much delay are you looking to add?

Regards,

Jennifer

Hi Jennifer,

I need to align the rising edge of the output with the SYSREF + ADLY to an other clock with at least 100ps accuracy. The digital delay gives me ~200ps steps so I need the analog delay get to 100ps accuracy. Therefore  I need a range of at least 100ps in the analog delay (better would be 200ps+) with a step size of at most 100ps. As far as I understand the analog delay can have a step size of ~13ps (0.5x range scale) with 32 steps (~400ps range). So I assume that this should be well within the capability of the analog delay.

Regards,

Christoph

Hi Jennifer,

Do you have any update on the matter?

Regards,

Christoph

Hi Christoph,

My apologies for the delay. The LMK5B designer has been out of office.  Let me work more internally to get more clarification on this issue.

Previously, we had observed SYSREF outputs to have poor duty cycle (less than 50 %) beyond 20 MHz outputs. The typical SYSREF use case we intended was for lower frequencies (such as 20 MHz and below). In terms of why SYSREF + ADLY causes the output to go away, it could be because the SYSREF frequency is beyond the intended frequency for ADLY.

Regards,

Jennifer