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LMK6H: Regarding PCIe jitter test result for LMK6H when it comes to different package and VDD

Tim Peng
Prodigy 150 points
Part Number: LMK6H

Tool/software:

Hi Team, 

For LMK6H, lots of jitter measurement result are listed in datasheet for HCSL (100 MHz) type LKM6H device. 

I am just curious if different package (DLE ann DLF) and different VDD(in associated with different VOH)  will make the jitter result different?  Do you have detail test condition to share? 

  • 0
    TI__Genius 12150 points

    Hi Tim, 

    The package size doesn't have a significant impact on the LMK6H jitter performance. For the datasheet specs, the typical conditions are usually taken at VDD = 3.3V and 25C, but the max specs consider the worst case variation over PVT. 

    For the PCIe jitter specs specifically, the minimum and maximum values also include variation across a sweep of simulated PLL loop filter settings at the receiver. You can see more details in our LMK6H PCIe compliance report here: https://www.ti.com/lit/an/snla445/snla445.pdf 

    Regards, 

    Connor 

  • 0 in reply to Connor Lewis
    Prodigy 150 points

    Hi Connor, 

    I am also looking for

    (1) random jitter ( Integrated RJ from 12 kHz to 20 MHz ) 

    (2) random jitter (Integrated Rj from 2 MHz to 20 MHz) 

    (3) deterministic jitter ( 0.75 to 10 MHz (offset) ) 

    (4) deterministic jitter ( 0.2 to 50 MHz (offset) ) 

    Do you have any idea how to find them in datasheet? 

  • +1 in reply to Tim Peng
    TI__Genius 12150 points

    We don't usually have separate specs for random vs. deterministic jitter, the RMS integrated jitter values on our datasheet includes both components. Regarding the different integration bands, I measured typical values for a 100MHz variant of LMK6H (see plot below). Let me know if this helps. 

    Regards, 

    Connor