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CDCE62005 LVPECL to HCSL output

JacobV1587
Intellectual 260 points
Other Parts Discussed in Thread: CDCE62005, CDCM61001

I use the CDCE62005 (LVPECL mode) to drive a HCSL CLK input.

I've used the interface as described in the CDCM61001 datasheet, page 26 (http://www.ti.com/lit/ds/symlink/cdcm61001.pdf)

On the output, I see an AM modulated signal with a high frequency of 100MHz (wanted) and a low frequency of 7.5 KHz. The amplitude varies between 400 mV-pp and
1.2 V-pp (single-ended). This effect is visible with a single-ended and differential probe.
What is possibly the reason of the variation in amplitude? All other LVDS outputs works fine.

I remove the two 150R resistors to GND, place a 100R termination resistor on both lines (such as LVDS termination), and the signal output is fine.
But does this type of termination reduce the reliability of the CDCE62005?

Thanks in advance

Jacob

 

  • 0
    TI__Expert 4150 points

    Hi Jacob,

    The circuit proposal shown on the CDCM61001 data sheet is approriate. I have no good explanation for what you have observed concerning the AM. 7.5kHz might come from your power supply somehow? Could it be that you have a lot of noise on your output power supply? If so, PECL is probably less immune than LVDS signaling to such noise due to being refrenced to the supply.

    The CDCE62005 outputs provide true PECL and LVDS signaling. If you put a 100-Ohm resistor across the P and N output terminal, you should not get any signal when you switch the output to PECL. It truly needs the 150-Ohm biasing to GND (or a 50-Ohm to Vcc/2, such as provided by a resistor divider of 130R and 87R). On the other hand, if your output was configured to LVDS, I wonder if a 150-Ohm resistor to GND could possibly cause a distortion. Again, 7.5kHz seem to make no sense when you generate 100MHz output clocks (and I assume your input clock and PFD frequency is also at several MHz).

     

    If my comments don't help soving this concern, feel free to send us your schematic and register settings to CDCE62005_inquiry@list.ti.com and we can review this further for you.

     

    Best regards. Falk Alicke

  • 0 in reply to Fritz
    TI__Expert 4150 points

    After further debuging of the circuit, customer identified that the input of the device driven by the CDCE62005 was configured as an output instead of an input. This explains the osciallation. The problem was resolved by configuring the input stage accordingly. Also, loop filter optimization was another critical item that became improved.

    Happy New 2012 to everyone! Your TI Clock Team