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LMK04832-SP: SEE Test Report

Candice Yui
Prodigy 10 points
Part Number: LMK04832-SP
Other Parts Discussed in Thread: LMK04832,

Tool/software:

Hope all is well.

I am looking at the TI’s LMK04832 SEE report and 2023 IEEE paper*.

 

Can you help with a few questions? 

 

  1. SEE test report page 9:  On the occasion that the status register contents were changed – was this accurately reporting the status (i.e. the PLL2 did go through a relock and Vtune DACs did change settings) or, were these contents false, induced by radiation?
  2. 2023 IEEE paper, page 4:  It is mentioned that the SEU could cause the output to be out of phase with the frequency prior to the event. Is the only way to return to the original phase is to reset the device?
  3. SEE test report pg. 6: Is it correct understanding that the configuration registers were programmed prior to the run and no scrubbing was employed during the test? Just like to validate that the reported results of no SEFI (i.e. no changes in any of the programmable registers) is applicable to a design without periodic rewriting of the configuration registers.

Thanks!

* Comparison of MSU and TAMU Heavy Ion Test Results and Evaluation Output Dependencies of SEUs for the LMK04832-SP by Kirby Kruckmeyer; Texas Instruments, Santa Clara, CA. USA, Ram Gooty; Texas Instruments, Tucson, AZ, USA, Samantha Williams; Texas Instruments, Dallas, TX, USA, Vibhu Vanjari; Texas Instruments, Santa Clara CA, USA, and Derek Payne; Texas Instruments, Federal Way, WA, USA

  • 0
    TI__Mastermind 33800 points
    1. Yes, PLL2 did go through a relock. This could be caused by a divider in the feedback loop resetting or something similar, particularly given that some configurations used zero-delay mode with the channel dividers in the feedback path, and the plots in the SEE report suggest these events can last on the order of µs (at least an order of magnitude longer than typical PLL2 PFD period). But because the registers did not change, neither did the divider values, and so the system returned to lock shortly after any such event.

      The VTUNE DACs did change settings, but looking at figure 3-4 in the SEE report, if we unpack the register values to the field values, we see that RB_DAC_VALUE field changed value from 0x1FF to 0x200 - i.e. it increased by a single bit, at midrange (i.e. nominal) voltage. The quantization of the DAC codes is 3.3V / 1024 = about 3mV/code. Between the loop bandwidth of PLL1 (around 100Hz), the typical duration of an SEU, and the magnitude of the observed code change, we can confidently conclude this is not related to radiation effects. The single bit increase is typically temperature-related settling of the VCXO frequency/voltage curve or the DAC sampling circuit. We regularly see this much shift outside of the radiation testing environment.

      The key takeaway is that the registers that we expect to remain non-volatile throughout the test do in fact remain non-volatile, undisturbed by any radiation events. The only registers which changed were an event latch that we expect to change and remain changed upon unlock event, and a live readback field that regularly varies by the observed magnitude in non-radiation environments.

    2. The phase errors are the result of divider resets (R, N, or output channel/SYSREF dividers) triggered by SEU. Re-synchronizing the dividers is possible without needing to fully reset or reprogram the device, and follows the typical synchronization procedure as outlined in the datasheet. To be clear, at a system level, synchronization is a complex enough problem that comprehensive resets may be a reasonable approach; but since the register states are preserved on the LMK04832, there is nothing fundamentally requiring LMK04832 to be reset and reprogrammed.

    3. Correct, no scrubbing or reprogramming was performed during the test. Registers were programmed once at test start. The SEFI results (i.e. no changes in any of the programmable registers) are applicable to a design without periodic rewriting of the configuration registers.