This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK05318B-Q1: Can't get outputs to mute, lock and sync...again

Part Number: LMK05318B-Q1
Other Parts Discussed in Thread: LMK05318B, LMK5B12204

Tool/software:

I had this working with my LMK12204s but for the life of me, I can't get it to work with the LMK05318B-Q1s.

I'm seeing really odd behavior.  The configs I've attached exhibit the following behavior...

When the registers are written live, I can issue a RESET_SW and the outputs will mute and less than a second later turn on locked to the input but not synced.  I can RESET_SW multiple times with the same result.

If I then issue a SYNC_SW command, the outputs will stay on but the DPLL will unlock for both phase and frequency and stay that way until I issue another RESET_SW.

Now if that's not strange enough, if I export the EEPROM map without changing anything in TICSPro, write the EEPROM, then do a PDN, the outputs come up unmuted and the DPLL unlocked. I then have to do a RESET_SW to get them back but they're still unsynced.

At one point during my fiddling, I got into a situation where after a RESET_SW the outputs would mute, then come back almost-synced BUT NOT LOCKED TO THE INPUT. A SYNC_SW would then sync them but they'd stay unlocked.

I've been running around in circles for 2 days now trying various combinations of options.  Even the exact options I used for the 12204s don't do the same thing on the 05318Bs.

Any help would be appreciated

.lmk05-10mhz-rev8-sync-mute.tcs

R0	0x000010
R1	0x00010B
R2	0x000235
R3	0x000332
R4	0x000404
R5	0x00050E
R6	0x000617
R7	0x00078E
R8	0x000802
R10	0x000AC8
R11	0x000B00
R12	0x000C1B
R13	0x000D08
R14	0x000E00
R15	0x000F00
R16	0x001000
R17	0x00111D
R18	0x0012FF
R19	0x001308
R20	0x001420
R21	0x001501
R22	0x001600
R23	0x001755
R24	0x0018FF
R25	0x0019F0
R26	0x001A00
R27	0x001B00
R28	0x001C01
R29	0x001D03
R30	0x001E40
R32	0x002044
R35	0x002300
R36	0x002403
R37	0x002500
R38	0x002600
R39	0x002702
R40	0x00280F
R41	0x002900
R42	0x002A11
R43	0x002BC2
R44	0x002C00
R45	0x002D0C
R46	0x002E88
R47	0x002F07
R48	0x003050
R49	0x00314A
R50	0x003200
R51	0x003300
R52	0x003400
R53	0x0035F9
R54	0x003600
R55	0x003700
R56	0x0038F9
R57	0x00393F
R58	0x003AF9
R59	0x003B3F
R60	0x003CF9
R61	0x003D3F
R62	0x003EF9
R63	0x003F3F
R64	0x004000
R65	0x004100
R66	0x004200
R67	0x0043F9
R68	0x004408
R69	0x004500
R70	0x004601
R71	0x004700
R72	0x004833
R73	0x004900
R74	0x004A00
R75	0x004B00
R76	0x004C00
R77	0x004D0F
R78	0x004E00
R79	0x004F11
R80	0x005080
R81	0x00510A
R82	0x005200
R83	0x005307
R84	0x005480
R85	0x005500
R86	0x005600
R87	0x00571E
R88	0x005884
R89	0x005980
R90	0x005A00
R91	0x005B14
R92	0x005C00
R93	0x005D07
R94	0x005E80
R95	0x005F00
R96	0x006000
R97	0x00611E
R98	0x006284
R99	0x006380
R100	0x006429
R101	0x006501
R102	0x006622
R103	0x00670F
R104	0x00681F
R105	0x006905
R106	0x006A00
R107	0x006B64
R108	0x006C00
R109	0x006D61
R110	0x006EA8
R111	0x006F00
R112	0x007000
R113	0x007100
R114	0x007200
R115	0x007303
R116	0x007401
R117	0x007500
R118	0x007600
R119	0x007700
R120	0x007800
R121	0x007900
R122	0x007A00
R123	0x007B28
R124	0x007C00
R125	0x007D11
R126	0x007E79
R127	0x007F7A
R128	0x008000
R129	0x008101
R130	0x008200
R131	0x008301
R132	0x008401
R133	0x008577
R134	0x008600
R135	0x00872B
R136	0x008800
R137	0x008928
R138	0x008AE5
R139	0x008B03
R140	0x008C02
R141	0x008D00
R142	0x008E01
R143	0x008F01
R144	0x009077
R145	0x009101
R146	0x009289
R147	0x009320
R149	0x00950D
R150	0x009600
R151	0x009701
R152	0x00980D
R153	0x009929
R154	0x009A24
R155	0x009B32
R156	0x009C01
R157	0x009D00
R158	0x009E00
R159	0x009F00
R160	0x00A0FC
R161	0x00A132
R162	0x00A200
R164	0x00A400
R165	0x00A500
R167	0x00A701
R178	0x00B200
R180	0x00B400
R181	0x00B500
R182	0x00B600
R183	0x00B700
R184	0x00B800
R185	0x00B905
R186	0x00BA08
R187	0x00BB00
R188	0x00BC00
R189	0x00BD00
R190	0x00BE98
R191	0x00BF00
R192	0x00C0F0
R193	0x00C12F
R194	0x00C22F
R195	0x00C300
R196	0x00C400
R197	0x00C544
R198	0x00C600
R199	0x00C700
R200	0x00C844
R201	0x00C900
R202	0x00CA00
R203	0x00CB00
R204	0x00CC38
R205	0x00CD00
R206	0x00CE00
R207	0x00CF38
R208	0x00D000
R209	0x00D114
R210	0x00D200
R211	0x00D316
R212	0x00D400
R213	0x00D528
R214	0x00D600
R215	0x00D72C
R216	0x00D80F
R217	0x00D900
R218	0x00DA00
R219	0x00DB13
R220	0x00DC13
R221	0x00DD00
R222	0x00DE03
R223	0x00DF0D
R224	0x00E048
R225	0x00E100
R226	0x00E200
R227	0x00E326
R228	0x00E426
R229	0x00E500
R230	0x00E606
R231	0x00E71A
R232	0x00E88F
R233	0x00E90B
R234	0x00EA0B
R235	0x00EB00
R236	0x00ECC3
R237	0x00ED50
R238	0x00EE00
R239	0x00EF00
R240	0x00F0C3
R241	0x00F150
R242	0x00F200
R243	0x00F300
R244	0x00F400
R249	0x00F921
R250	0x00FA00
R251	0x00FB23
R252	0x00FC2D
R253	0x00FD00
R254	0x00FE00
R255	0x00FF00
R256	0x010000
R257	0x010101
R258	0x010200
R259	0x010301
R260	0x010402
R261	0x010580
R262	0x010600
R263	0x010700
R264	0x010800
R265	0x010901
R266	0x010AF4
R267	0x010BA0
R268	0x010C0C
R269	0x010D03
R270	0x010E02
R271	0x010FB6
R272	0x011000
R273	0x011100
R274	0x011200
R275	0x01130E
R276	0x01140C
R277	0x01150E
R278	0x011609
R279	0x011708
R280	0x011809
R281	0x011907
R282	0x011A0D
R283	0x011B07
R284	0x011C1E
R285	0x011D1E
R286	0x011E02
R287	0x011F70
R288	0x012003
R289	0x0121EC
R290	0x012203
R291	0x01230A
R292	0x012409
R293	0x012501
R294	0x012600
R295	0x01272C
R296	0x012806
R297	0x01290A
R298	0x012A06
R299	0x012B01
R300	0x012C00
R301	0x012D1C
R302	0x012E20
R303	0x012F01
R304	0x013000
R305	0x013100
R306	0x013200
R307	0x013300
R308	0x01343E
R309	0x013580
R310	0x013600
R311	0x013700
R312	0x013800
R313	0x013900
R314	0x013A00
R315	0x013B00
R316	0x013C00
R317	0x013D00
R318	0x013E00
R319	0x013F03
R320	0x014000
R321	0x01410A
R322	0x014200
R323	0x01430E
R324	0x0144A6
R325	0x014500
R326	0x014600
R327	0x014798
R328	0x014896
R329	0x014980
R330	0x014A00
R331	0x014B64
R332	0x014C00
R333	0x014D00
R334	0x014E3D
R335	0x014F09
R336	0x015000
R337	0x015198
R338	0x015296
R339	0x015380
R340	0x015400
R341	0x015500
R342	0x015600
R343	0x015700
R344	0x015800
R345	0x015900
R346	0x015A02
R347	0x015B00
R348	0x015C00
R349	0x015D00
R350	0x015E00
R351	0x015F00
R352	0x016000
R357	0x016528
R367	0x016F00
R411	0x019B0C
[EEPROM_IMAGE]
COUNT=253
DATE_TIME=2025-07-02, 15:56:07
EEPROM_IMG_IDX00=4
EEPROM_IMG_IDX01=14
EEPROM_IMG_IDX02=23
EEPROM_IMG_IDX03=142
EEPROM_IMG_IDX04=50
EEPROM_IMG_IDX05=1
EEPROM_IMG_IDX06=137
EEPROM_IMG_IDX07=32
EEPROM_IMG_IDX08=0
EEPROM_IMG_IDX09=100
EEPROM_IMG_IDX10=200
EEPROM_IMG_IDX11=0
EEPROM_IMG_IDX12=120
EEPROM_IMG_IDX13=0
EEPROM_IMG_IDX14=127
EEPROM_IMG_IDX15=250
EEPROM_IMG_IDX16=42
EEPROM_IMG_IDX17=255
EEPROM_IMG_IDX18=248
EEPROM_IMG_IDX19=0
EEPROM_IMG_IDX20=0
EEPROM_IMG_IDX21=33
EEPROM_IMG_IDX22=208
EEPROM_IMG_IDX23=13
EEPROM_IMG_IDX24=41
EEPROM_IMG_IDX25=240
EEPROM_IMG_IDX26=53
EEPROM_IMG_IDX27=32
EEPROM_IMG_IDX28=6
EEPROM_IMG_IDX29=2
EEPROM_IMG_IDX30=15
EEPROM_IMG_IDX31=0
EEPROM_IMG_IDX32=156
EEPROM_IMG_IDX33=32
EEPROM_IMG_IDX34=50
EEPROM_IMG_IDX35=32
EEPROM_IMG_IDX36=61
EEPROM_IMG_IDX37=9
EEPROM_IMG_IDX38=64
EEPROM_IMG_IDX39=0
EEPROM_IMG_IDX40=0
EEPROM_IMG_IDX41=249
EEPROM_IMG_IDX42=0
EEPROM_IMG_IDX43=3
EEPROM_IMG_IDX44=228
EEPROM_IMG_IDX45=255
EEPROM_IMG_IDX46=228
EEPROM_IMG_IDX47=255
EEPROM_IMG_IDX48=228
EEPROM_IMG_IDX49=255
EEPROM_IMG_IDX50=228
EEPROM_IMG_IDX51=252
EEPROM_IMG_IDX52=0
EEPROM_IMG_IDX53=0
EEPROM_IMG_IDX54=3
EEPROM_IMG_IDX55=228
EEPROM_IMG_IDX56=32
EEPROM_IMG_IDX57=0
EEPROM_IMG_IDX58=0
EEPROM_IMG_IDX59=3
EEPROM_IMG_IDX60=192
EEPROM_IMG_IDX61=17
EEPROM_IMG_IDX62=0
EEPROM_IMG_IDX63=20
EEPROM_IMG_IDX64=0
EEPROM_IMG_IDX65=60
EEPROM_IMG_IDX66=0
EEPROM_IMG_IDX67=0
EEPROM_IMG_IDX68=3
EEPROM_IMG_IDX69=208
EEPROM_IMG_IDX70=144
EEPROM_IMG_IDX71=0
EEPROM_IMG_IDX72=5
EEPROM_IMG_IDX73=0
EEPROM_IMG_IDX74=7
EEPROM_IMG_IDX75=128
EEPROM_IMG_IDX76=0
EEPROM_IMG_IDX77=0
EEPROM_IMG_IDX78=122
EEPROM_IMG_IDX79=18
EEPROM_IMG_IDX80=0
EEPROM_IMG_IDX81=164
EEPROM_IMG_IDX82=165
EEPROM_IMG_IDX83=239
EEPROM_IMG_IDX84=148
EEPROM_IMG_IDX85=25
EEPROM_IMG_IDX86=1
EEPROM_IMG_IDX87=134
EEPROM_IMG_IDX88=160
EEPROM_IMG_IDX89=0
EEPROM_IMG_IDX90=0
EEPROM_IMG_IDX91=0
EEPROM_IMG_IDX92=0
EEPROM_IMG_IDX93=12
EEPROM_IMG_IDX94=128
EEPROM_IMG_IDX95=0
EEPROM_IMG_IDX96=0
EEPROM_IMG_IDX97=0
EEPROM_IMG_IDX98=0
EEPROM_IMG_IDX99=8
EEPROM_IMG_IDX100=4
EEPROM_IMG_IDX101=31
EEPROM_IMG_IDX102=197
EEPROM_IMG_IDX103=96
EEPROM_IMG_IDX104=5
EEPROM_IMG_IDX105=28
EEPROM_IMG_IDX106=160
EEPROM_IMG_IDX107=97
EEPROM_IMG_IDX108=0
EEPROM_IMG_IDX109=65
EEPROM_IMG_IDX110=252
EEPROM_IMG_IDX111=0
EEPROM_IMG_IDX112=0
EEPROM_IMG_IDX113=0
EEPROM_IMG_IDX114=0
EEPROM_IMG_IDX115=0
EEPROM_IMG_IDX116=208
EEPROM_IMG_IDX117=0
EEPROM_IMG_IDX118=0
EEPROM_IMG_IDX119=2
EEPROM_IMG_IDX120=96
EEPROM_IMG_IDX121=190
EEPROM_IMG_IDX122=240
EEPROM_IMG_IDX123=0
EEPROM_IMG_IDX124=17
EEPROM_IMG_IDX125=0
EEPROM_IMG_IDX126=0
EEPROM_IMG_IDX127=68
EEPROM_IMG_IDX128=0
EEPROM_IMG_IDX129=0
EEPROM_IMG_IDX130=56
EEPROM_IMG_IDX131=0
EEPROM_IMG_IDX132=0
EEPROM_IMG_IDX133=224
EEPROM_IMG_IDX134=0
EEPROM_IMG_IDX135=160
EEPROM_IMG_IDX136=1
EEPROM_IMG_IDX137=96
EEPROM_IMG_IDX138=5
EEPROM_IMG_IDX139=0
EEPROM_IMG_IDX140=11
EEPROM_IMG_IDX141=60
EEPROM_IMG_IDX142=0
EEPROM_IMG_IDX143=4
EEPROM_IMG_IDX144=196
EEPROM_IMG_IDX145=192
EEPROM_IMG_IDX146=12
EEPROM_IMG_IDX147=53
EEPROM_IMG_IDX148=32
EEPROM_IMG_IDX149=0
EEPROM_IMG_IDX150=9
EEPROM_IMG_IDX151=137
EEPROM_IMG_IDX152=128
EEPROM_IMG_IDX153=24
EEPROM_IMG_IDX154=106
EEPROM_IMG_IDX155=61
EEPROM_IMG_IDX156=107
EEPROM_IMG_IDX157=1
EEPROM_IMG_IDX158=134
EEPROM_IMG_IDX159=160
EEPROM_IMG_IDX160=0
EEPROM_IMG_IDX161=3
EEPROM_IMG_IDX162=13
EEPROM_IMG_IDX163=64
EEPROM_IMG_IDX164=0
EEPROM_IMG_IDX165=0
EEPROM_IMG_IDX166=8
EEPROM_IMG_IDX167=66
EEPROM_IMG_IDX168=203
EEPROM_IMG_IDX169=128
EEPROM_IMG_IDX170=0
EEPROM_IMG_IDX171=0
EEPROM_IMG_IDX172=0
EEPROM_IMG_IDX173=128
EEPROM_IMG_IDX174=0
EEPROM_IMG_IDX175=40
EEPROM_IMG_IDX176=0
EEPROM_IMG_IDX177=0
EEPROM_IMG_IDX178=0
EEPROM_IMG_IDX179=62
EEPROM_IMG_IDX180=148
EEPROM_IMG_IDX181=48
EEPROM_IMG_IDX182=117
EEPROM_IMG_IDX183=176
EEPROM_IMG_IDX184=0
EEPROM_IMG_IDX185=0
EEPROM_IMG_IDX186=230
EEPROM_IMG_IDX187=57
EEPROM_IMG_IDX188=40
EEPROM_IMG_IDX189=73
EEPROM_IMG_IDX190=218
EEPROM_IMG_IDX191=127
EEPROM_IMG_IDX192=122
EEPROM_IMG_IDX193=112
EEPROM_IMG_IDX194=251
EEPROM_IMG_IDX195=48
EEPROM_IMG_IDX196=169
EEPROM_IMG_IDX197=66
EEPROM_IMG_IDX198=193
EEPROM_IMG_IDX199=138
EEPROM_IMG_IDX200=25
EEPROM_IMG_IDX201=3
EEPROM_IMG_IDX202=144
EEPROM_IMG_IDX203=2
EEPROM_IMG_IDX204=0
EEPROM_IMG_IDX205=0
EEPROM_IMG_IDX206=0
EEPROM_IMG_IDX207=31
EEPROM_IMG_IDX208=64
EEPROM_IMG_IDX209=0
EEPROM_IMG_IDX210=0
EEPROM_IMG_IDX211=0
EEPROM_IMG_IDX212=0
EEPROM_IMG_IDX213=0
EEPROM_IMG_IDX214=0
EEPROM_IMG_IDX215=0
EEPROM_IMG_IDX216=0
EEPROM_IMG_IDX217=0
EEPROM_IMG_IDX218=3
EEPROM_IMG_IDX219=0
EEPROM_IMG_IDX220=20
EEPROM_IMG_IDX221=0
EEPROM_IMG_IDX222=117
EEPROM_IMG_IDX223=48
EEPROM_IMG_IDX224=0
EEPROM_IMG_IDX225=19
EEPROM_IMG_IDX226=18
EEPROM_IMG_IDX227=208
EEPROM_IMG_IDX228=0
EEPROM_IMG_IDX229=25
EEPROM_IMG_IDX230=0
EEPROM_IMG_IDX231=0
EEPROM_IMG_IDX232=61
EEPROM_IMG_IDX233=9
EEPROM_IMG_IDX234=2
EEPROM_IMG_IDX235=98
EEPROM_IMG_IDX236=90
EEPROM_IMG_IDX237=0
EEPROM_IMG_IDX238=0
EEPROM_IMG_IDX239=0
EEPROM_IMG_IDX240=0
EEPROM_IMG_IDX241=0
EEPROM_IMG_IDX242=0
EEPROM_IMG_IDX243=16
EEPROM_IMG_IDX244=0
EEPROM_IMG_IDX245=0
EEPROM_IMG_IDX246=0
EEPROM_IMG_IDX247=0
EEPROM_IMG_IDX248=0

[META]
DEVICE=LMK05318B
DATA=SRAM
WORD_SIZE_BITS=24
RAMDAT_ADDR=R162[7:0]
MEMDAT_ADDR=R159[4:0], R159[7:0]
PART_ID_ADDR=R3[7:0], R2[7:0]
PART_ID_VALUE=0x1135

[FREQUENCY]
XO=12800000

  • Just to add a bit more info. I'm using a single 3.3v power supply but I also have a 4.7uf cap to VDD on the PDN pin which with the 200K internal pull-up should give a bit of a delay and the goal I forgot to state above is startup muted until locked and synced without having to issue an explicit SYNC.

    Also, I had noticed that when the DPLL fails to lock, PRIREF_VALSTAT=false but LOR_MISSCLK, LOR_FREQ and LOR_AMP are also false.  What other registers can I check to determine why PRIREF_VALSTAT is false?

    Another thing that would be helpful is a troubleshooting guide.  There's tons of great info in the data sheets but is more "reference" than "guide".  My question above about PRIREF_VALSTAT would be a good topic.  PRIREF_VALSTAT isn't even mentioned in the data sheets.  Another topic that would be good would be what parameters to look at to get a reliable DPLL phase or frequency lock or what to look at if you have a frequency lock but not a phase lock. I've had that several times.  Yet another would be what to adjust  to make the DPLL more tolerant of input reference jitter.

  • Hi George,

    Hm, I would expect the LMK5B12204 config to translate into the LMK05318B config without issue.

    Can you please provide the .tcs file you use for LMK5B12204 that is giving the results you want?

    Regards,

    Jennifer

  • OK, here are 4 tcs files...

    lmk5b-10mhz-rev5-sync-mute.tcs: I believe this is the one I had fully working with the 12204s but I don't have any left I can test with.  When written to a 05318B, OUT5 comes up locked but not OUT6.  After a SYNC_SW, they both come up locked and synced.  OUT7 and OUT4 don't come up at all which is expected.

    lmk05-10mhz-rev8-base.tcs: This is a base config with no sync or mute.  The outputs come up unmuted and unlocked for just less than a second then lock and remain stable,  A RESET_SW just unlocks them for about a second then they lock again and stay stable.

    lmk05-10mhz-rev8-mute.tcs:  This is the same as as the rev8-base plus CHx_MUTE set to Force Low and MUTE_APLL1_LOCK and MUTE_DPLL_FRLOCK set.  This works as expected.  The outputs start muted and less than a second later come up locked.

    lmk05-10mhz-rev8-sync-mute.tcs:  This is one giving me fits.  This is the same as rev8-mute plus PLL1_P1_SYNC_EN, SYNC_AUTO_APLL and SYNC_MUTE turned on. I did manage to get past the bizarre behavior I related above (it might have been a bad reflow).  Now in this one, the outputs all start muted, then less than a second later only OUT6 comes up locked.  The other outputs don't come up until I issue a SYNC_SW command, then they all do come up locked and synced.  I thought that SYNC_AUTO_APLL was the key to getting them all to come up synced but I tried various combinations of it plus PLL1_P1_SYNC_EN and SYNC_MUTE but the closest I could come was  what I just described with all 3 enabled.

    Here are the files:

    lmk5b-10mhz-rev5-sync-mute.tcs

    lmk05-10mhz-rev8-base.tcs

    lmk05-10mhz-rev8-mute.tcs

    5076.lmk05-10mhz-rev8-sync-mute.tcs

  • Hi George,

    Please allow us time to review. We will get back to you early next week after the US holidays for 4th of July.

    Regards,
    Jennifer

  • No worries!  I'm off tomorrow as well.

  • Well, I couldn't leave it alone even though I have the day off.  I found the secret combination though...

    It was setting PLL1_P1_SYNC_EN that was preventing the auto-sync on startup/reset.

    Jennifer, No need to look at the files I posted earlier.  I do have one question though...  SYNC_AUTO_DPLL is listed in the register reference as R12[5] but it doesn't show up in TICS Pro at all.  It doesn't seem to do anything (even when the 0xA7 mask is changed to 0x87) so I was wondering if it was implemented.

  • Hi George,

    Yes, the SYNC_AUTO_DPLL does not not anything from my recent findings

    https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1523650/lmk5b12204-higher-current-draw-when-started-from-eeprom-than-rom/

    We are correcting the description to clarify that bit is a don't care/reserved. We are making updates to the LMK05318B and LMK5B12204 programming guides. There was a recent release for LMK05318B guide but we are making further updates to release again soon.

    Regards,

    Jennifer