LMK3H0102-Q1: How to read the chip address through I2C in OTP mode and then configure it to I2C mode

Hello TI:

When we use the LMK3H0102 clock chip output to light the screen, we encounter water ripple on the 15-inch screen display screen, and the 12.9-inch screen display screen is normal.

We have two screens in total, one is 15-inch screen, LMK3H0102 outputs 177.978240MHZ, and one is 12.9-inch small screen, LMK3H0102 outputs 136.903200MHZ. The specific register configuration of LMK3H0102 is referenced as above internal link, all provided by TI. Then the serializer is DS90UB941, the deserializer is DS90UB948,

When investigating the problem of water ripples on the screen with 15-inch screen, the current investigation found the following:

Through the verification below, we follow the external timing and external clks used by the water ripple problem. Moreover, by adjusting the output porch value of the SOC, that is, timing or adjusting the output clks of the LMK3H0102 chip fluctuations around 177M, which will cause the water ripple phenomenon to become more serious.

I would like to consult the following questions:

Question 1: There is a difference between the external reference clock and the DSI clock. What will be done internally in 941? Will it be synchronized with the DSI clock?
Question 2: What is the difference between the external reference clock and the DSI clock? Does it depend on the DS90UB941 or the screen?
Question 3: When 941 receives the porch value of external timing, is there a corresponding register that can be read out? If so, can I parse the porch value by reading the 941 register and compare the porch output by soc? Please provide the corresponding register?
Question 4: There is no water ripple problem when using the 12.9-inch screen. There is no water ripple problem when using the 15-inch screen. I dumped the dsi register, normal register and remote register. At present, the difference in remote registers is quite large. Please help with comparison and analysis.

12.9 panel:







remote ds90ub948 register 15 panel:

[REGISTERS]
Device = ALP Nano 1 - DS90UB948, Connector 1
Comments = "7-9-ref-clk-remote-register-dump-flick"
Date = 07/09/2025
Time = 10:16:51
Reg = 0,0x0000,0x58
Reg = 0,0x0001,0x04
Reg = 0,0x0002,0x90
Reg = 0,0x0003,0xF6
Reg = 0,0x0004,0x02
Reg = 0,0x0005,0x1E
Reg = 0,0x0006,0x06
Reg = 0,0x0007,0x34
Reg = 0,0x0008,0x00
Reg = 0,0x0009,0x00
Reg = 0,0x000A,0x00
Reg = 0,0x000B,0x00
Reg = 0,0x000C,0x00
Reg = 0,0x000D,0x00
Reg = 0,0x000E,0x00
Reg = 0,0x000F,0x00
Reg = 0,0x0010,0x00
Reg = 0,0x0011,0x00
Reg = 0,0x0012,0x00
Reg = 0,0x0013,0x00
Reg = 0,0x0014,0x00
Reg = 0,0x0015,0x00
Reg = 0,0x0016,0x00
Reg = 0,0x0017,0x00
Reg = 0,0x0018,0x00
Reg = 0,0x0019,0x01
Reg = 0,0x001A,0x11
Reg = 0,0x001B,0x00
Reg = 0,0x001C,0x33
Reg = 0,0x001D,0x13
Reg = 0,0x001E,0x33
Reg = 0,0x001F,0x03
Reg = 0,0x0020,0x11
Reg = 0,0x0021,0x11
Reg = 0,0x0022,0x90
Reg = 0,0x0023,0xA0
Reg = 0,0x0024,0x02
Reg = 0,0x0025,0x00
Reg = 0,0x0026,0x83
Reg = 0,0x0027,0x84
Reg = 0,0x0028,0x94
Reg = 0,0x0029,0xE3
Reg = 0,0x002A,0x00
Reg = 0,0x002B,0x00
Reg = 0,0x002C,0x00
Reg = 0,0x002D,0x00
Reg = 0,0x002E,0x00
Reg = 0,0x002F,0x00
Reg = 0,0x0030,0x00
Reg = 0,0x0031,0x00
Reg = 0,0x0032,0x90
Reg = 0,0x0033,0x25
Reg = 0,0x0034,0x0B
Reg = 0,0x0035,0x30
Reg = 0,0x0036,0x00
Reg = 0,0x0037,0x88
Reg = 0,0x0038,0x00
Reg = 0,0x0039,0x00
Reg = 0,0x003A,0x00
Reg = 0,0x003B,0x00
Reg = 0,0x003C,0x20
Reg = 0,0x003D,0xE0
Reg = 0,0x003E,0x23
Reg = 0,0x003F,0x00
Reg = 0,0x0040,0x43
Reg = 0,0x0041,0x03
Reg = 0,0x0042,0x03
Reg = 0,0x0043,0x00
Reg = 0,0x0044,0x01
Reg = 0,0x0045,0x60
Reg = 0,0x0046,0x00
Reg = 0,0x0047,0x00
Reg = 0,0x0048,0x0F
Reg = 0,0x0049,0x00
Reg = 0,0x004A,0x00
Reg = 0,0x004B,0x08
Reg = 0,0x004C,0x00
Reg = 0,0x004D,0x00
Reg = 0,0x004E,0x63
Reg = 0,0x004F,0x00
Reg = 0,0x0050,0x03
Reg = 0,0x0051,0x10
Reg = 0,0x0052,0x00
Reg = 0,0x0053,0x01
Reg = 0,0x0054,0x80
Reg = 0,0x0055,0x00
Reg = 0,0x0056,0x08
Reg = 0,0x0057,0x00
Reg = 0,0x0058,0x00
Reg = 0,0x0059,0x7F
Reg = 0,0x005A,0x20
Reg = 0,0x005B,0x20
Reg = 0,0x005C,0x18
Reg = 0,0x005D,0x00
Reg = 0,0x005E,0x00
Reg = 0,0x005F,0x00
Reg = 0,0x0060,0x00
Reg = 0,0x0061,0x00
Reg = 0,0x0062,0x00
Reg = 0,0x0063,0x00
Reg = 0,0x0064,0x10
Reg = 0,0x0065,0x00
Reg = 0,0x0066,0x00
Reg = 0,0x0067,0x00
Reg = 0,0x0068,0x00
Reg = 0,0x0069,0x00
Reg = 0,0x006E,0x00
Reg = 0,0x006F,0x00
Reg = 0,0x0070,0x00
Reg = 0,0x0071,0x00
Reg = 0,0x0072,0x00
Reg = 0,0x0073,0x07
Reg = 0,0x0074,0x07
Reg = 0,0x0075,0x08
Reg = 0,0x0076,0x00
Reg = 0,0x0077,0x00
Reg = 0,0x0078,0x00
Reg = 0,0x0079,0x00
Reg = 0,0x007A,0x00
Reg = 0,0x007B,0x00
Reg = 0,0x007C,0x02
Reg = 0,0x0080,0x00
Reg = 0,0x0081,0x00
Reg = 0,0x0082,0x00
Reg = 0,0x0083,0x00
Reg = 0,0x0084,0x00
Reg = 0,0x0090,0x00
Reg = 0,0x0091,0x00
Reg = 0,0x0092,0x00
Reg = 0,0x0093,0x00
Reg = 0,0x0094,0x00
Reg = 0,0x0098,0x00
Reg = 0,0x0099,0x00
Reg = 0,0x009A,0x00
Reg = 0,0x009B,0x00
Reg = 0,0x009C,0x00
Reg = 0,0x009D,0x00
Reg = 0,0x009E,0x00
Reg = 0,0x009F,0x00
Reg = 0,0x00C0,0x08
Reg = 0,0x00C1,0x00
Reg = 0,0x00C3,0x00
Reg = 0,0x00C4,0x02
Reg = 0,0x00C5,0x00
Reg = 0,0x00C8,0xC0
Reg = 0,0x00C9,0x00
Reg = 0,0x00CA,0x00
Reg = 0,0x00CB,0x00
Reg = 0,0x00CC,0x00
Reg = 0,0x00E0,0x00
Reg = 0,0x00E1,0x00
Reg = 0,0x00E2,0x00
Reg = 0,0x00E3,0x00
Reg = 0,0x00E8,0x00
Reg = 0,0x00E9,0x00
Reg = 0,0x00EA,0x00
Reg = 0,0x00F0,0x5F
Reg = 0,0x00F1,0x55
Reg = 0,0x00F2,0x42
Reg = 0,0x00F3,0x39
Reg = 0,0x00F4,0x34
Reg = 0,0x00F5,0x38
Reg = 0,0x00F6,0x00
Reg = 0,0x00F8,0x00
Reg = 0,0x00F9,0x00


remote ds90ub948 register  12.9 panel:
[REGISTERS]
Device = ALP Nano 1 - DS90UB948, Connector 1
Comments = "7-9-ref-clk-remote-register-dump-12.9-noflick"
Date = 07/09/2025
Time = 16:45:37
Reg = 0,0x0000,0x58
Reg = 0,0x0001,0x04
Reg = 0,0x0002,0x00
Reg = 0,0x0003,0xF0
Reg = 0,0x0004,0xFE
Reg = 0,0x0005,0x1E
Reg = 0,0x0006,0x00
Reg = 0,0x0007,0x34
Reg = 0,0x0008,0x00
Reg = 0,0x0009,0x00
Reg = 0,0x000A,0x00
Reg = 0,0x000B,0x00
Reg = 0,0x000C,0x00
Reg = 0,0x000D,0x00
Reg = 0,0x000E,0x00
Reg = 0,0x000F,0x00
Reg = 0,0x0010,0x00
Reg = 0,0x0011,0x00
Reg = 0,0x0012,0x00
Reg = 0,0x0013,0x00
Reg = 0,0x0014,0x00
Reg = 0,0x0015,0x00
Reg = 0,0x0016,0x00
Reg = 0,0x0017,0x00
Reg = 0,0x0018,0x00
Reg = 0,0x0019,0x01
Reg = 0,0x001A,0x00
Reg = 0,0x001B,0xF2
Reg = 0,0x001C,0x33
Reg = 0,0x001D,0x13
Reg = 0,0x001E,0x33
Reg = 0,0x001F,0x03
Reg = 0,0x0020,0x00
Reg = 0,0x0021,0x00
Reg = 0,0x0022,0x40
Reg = 0,0x0023,0x20
Reg = 0,0x0024,0x08
Reg = 0,0x0025,0x00
Reg = 0,0x0026,0x83
Reg = 0,0x0027,0x84
Reg = 0,0x0028,0x11
Reg = 0,0x0029,0x00
Reg = 0,0x002A,0x00
Reg = 0,0x002B,0x00
Reg = 0,0x002C,0x00
Reg = 0,0x002D,0x00
Reg = 0,0x002E,0x00
Reg = 0,0x002F,0x00
Reg = 0,0x0030,0x00
Reg = 0,0x0031,0x00
Reg = 0,0x0032,0x90
Reg = 0,0x0033,0x25
Reg = 0,0x0034,0x03
Reg = 0,0x0035,0x00
Reg = 0,0x0036,0x00
Reg = 0,0x0037,0x8C
Reg = 0,0x0038,0x00
Reg = 0,0x0039,0x00
Reg = 0,0x003A,0x00
Reg = 0,0x003B,0x01
Reg = 0,0x003C,0x20
Reg = 0,0x003D,0xE0
Reg = 0,0x003E,0x23
Reg = 0,0x003F,0x00
Reg = 0,0x0040,0x43
Reg = 0,0x0041,0x03
Reg = 0,0x0042,0x03
Reg = 0,0x0043,0x00
Reg = 0,0x0044,0x60
Reg = 0,0x0045,0x88
Reg = 0,0x0046,0x00
Reg = 0,0x0047,0x00
Reg = 0,0x0048,0x0F
Reg = 0,0x0049,0x80
Reg = 0,0x004A,0x00
Reg = 0,0x004B,0x0B
Reg = 0,0x004C,0x00
Reg = 0,0x004D,0x00
Reg = 0,0x004E,0x63
Reg = 0,0x004F,0x00
Reg = 0,0x0050,0x03
Reg = 0,0x0051,0x10
Reg = 0,0x0052,0x00
Reg = 0,0x0053,0x01
Reg = 0,0x0054,0x80
Reg = 0,0x0055,0x00
Reg = 0,0x0056,0x00
Reg = 0,0x0057,0x00
Reg = 0,0x0058,0x00
Reg = 0,0x0059,0x7F
Reg = 0,0x005A,0x20
Reg = 0,0x005B,0x20
Reg = 0,0x005C,0x18
Reg = 0,0x005D,0x00
Reg = 0,0x005E,0x00
Reg = 0,0x005F,0x00
Reg = 0,0x0060,0x00
Reg = 0,0x0061,0x00
Reg = 0,0x0062,0x00
Reg = 0,0x0063,0x00
Reg = 0,0x0064,0x00
Reg = 0,0x0065,0x04
Reg = 0,0x0066,0x0E
Reg = 0,0x0067,0x03
Reg = 0,0x0068,0x00
Reg = 0,0x0069,0x00
Reg = 0,0x006E,0x08
Reg = 0,0x006F,0x00
Reg = 0,0x0070,0x00
Reg = 0,0x0071,0x00
Reg = 0,0x0072,0x00
Reg = 0,0x0073,0x07
Reg = 0,0x0074,0x07
Reg = 0,0x0075,0x08
Reg = 0,0x0076,0x00
Reg = 0,0x0077,0x00
Reg = 0,0x0078,0x00
Reg = 0,0x0079,0x00
Reg = 0,0x007A,0x00
Reg = 0,0x007B,0x00
Reg = 0,0x007C,0x02
Reg = 0,0x0080,0x00
Reg = 0,0x0081,0x00
Reg = 0,0x0082,0x00
Reg = 0,0x0083,0x00
Reg = 0,0x0084,0x00
Reg = 0,0x0090,0x00
Reg = 0,0x0091,0x00
Reg = 0,0x0092,0x00
Reg = 0,0x0093,0x00
Reg = 0,0x0094,0x00
Reg = 0,0x0098,0x00
Reg = 0,0x0099,0x00
Reg = 0,0x009A,0x00
Reg = 0,0x009B,0x00
Reg = 0,0x009C,0x00
Reg = 0,0x009D,0x00
Reg = 0,0x009E,0x00
Reg = 0,0x009F,0x00
Reg = 0,0x00C0,0x00
Reg = 0,0x00C1,0x00
Reg = 0,0x00C3,0x00
Reg = 0,0x00C4,0x00
Reg = 0,0x00C5,0x00
Reg = 0,0x00C8,0xC0
Reg = 0,0x00C9,0x00
Reg = 0,0x00CA,0x00
Reg = 0,0x00CB,0x00
Reg = 0,0x00CC,0x00
Reg = 0,0x00E0,0x00
Reg = 0,0x00E1,0x00
Reg = 0,0x00E2,0x00
Reg = 0,0x00E3,0x00
Reg = 0,0x00E8,0x00
Reg = 0,0x00E9,0x00
Reg = 0,0x00EA,0x00
Reg = 0,0x00F0,0x5F
Reg = 0,0x00F1,0x55
Reg = 0,0x00F2,0x42
Reg = 0,0x00F3,0x39
Reg = 0,0x00F4,0x34
Reg = 0,0x00F5,0x38
Reg = 0,0x00F6,0x00
Reg = 0,0x00F8,0x00
Reg = 0,0x00F9,0x00

Hello,

There is NO means of accessing the I2C interface in OTP mode. This is why they are listed as two distinct modes of operation. You can start the device in EITHER I2C mode or OTP mode. You cannot switch between these without power cycling the device, with Pin 15 configured as needed prior to applying power.

If I2C is required, start the device in I2C mode with Pin 15 pulled low. This is functionally equivalent to starting up on OTP Page 0 from a register perspective.

I will reassign this to the proper team for the remaining questions.

Thanks,
Kadeem

Hello:

Currently, REF_CTRL is high and FMT_ADDR pin is high. Can the I2C address of the LMK3H0102 chip be read on the software? However, the I2C address is 0x68 through the TICS PRO tool. What's going on? Is it the address that OTP fixedly writes? So can this address be read by the external MCU through the I2C SCL SDA?

?? ? said:

Question 1: There is a difference between the external reference clock and the DSI clock. What will be done internally in 941? Will it be synchronized with the DSI clock?

The 941 can either run on the reference clock or the DSI clock. The system can run off the DSI clock but customers sometimes want to utilize the reference clock as their input for lower jitter/noise.

?? ? said:

Question 2: What is the difference between the external reference clock and the DSI clock? Does it depend on the DS90UB941 or the screen?

The DSI clock and the reference clock frequency will depend on pixel clock rate of the screen. 

?? ? said:

Question 3: When 941 receives the porch value of external timing, is there a corresponding register that can be read out? If so, can I parse the porch value by reading the 941 register and compare the porch output by soc? Please provide the corresponding register?

You cannot read the porch values directly from the serializer

?? ? said:

Question 4: There is no water ripple problem when using the 12.9-inch screen. There is no water ripple problem when using the 15-inch screen. I dumped the dsi register, normal register and remote register. At present, the difference in remote registers is quite large. Please help with comparison and analysis.

What are you referring to with the "remote registers", are you talking about the registers from the DES? Could you also provide the external timing from the DSI input?

Best,

Zain A

Yes I attached is the DES, it is different between 12.9 panel and 15 panel

The 15 panel external timing is below:

119 static struct dsi_panel_param dsi_panel_parameter[] = {
120 //15inch
121 {
122 .t_clk_post = 0x0e,
123 .t_clk_pre = 0x1e,
124 .h_active = 2240,
125 .v_active = 1260,
126 .h_front_porch = 24,
127 .h_back_porch = 40,
128 .h_sync_width = 28,
129 .v_front_porch = 6,
130 .v_back_porch = 4,
131 .v_sync_width = 2,
132 },

dsi clock = v total * h total * fps = (1260+6+4+2) * (2240+24+40+28) * 60 = 177,978,240 HZ

The 12.9 panel external timing is below:

//[12.9]inch
{
.t_clk_post = 0x0c,
.t_clk_pre = 0x18,
.h_active = 1920,
.v_active = 1080,
.h_front_porch = 38,
.h_back_porch = 36,
.h_sync_width = 36,
.v_front_porch = 34,
.v_back_porch = 8,
.v_sync_width = 2,
},

dsi clock = (1080+34+8+2) * (1920+38+36+36) * 60 = 136,903,200 HZ

Can you find some of the main register differences between DES 948 from the 15-inch screen and 12.9-inch screen? I understand the current water ripple problem. It may be caused by the abnormal synchronization of external ref clk and external timing, but the 12.9-inch screen display is normal, so I also suspect that the screen-end deserializer configuration is different.

Hello Zain：

Can you help me see how to investigate the water ripple problem? The specific situation is as follows:

Use the clock of LMK3H0102 as the ref clk of the DS90UB941 serializer, and is paired with the DS90UB948 deserializer on the screen. It displays normally on the 12.9-inch screen, and water ripple problems occur on the 15-inch screen.

Hi, 

I noticed that in both cases with the 941 SER, you are getting CRC errors in both cases from register 0xC. Just to clarify in both cases with the 12.9 in and 15in displays, are you using the same 948 or two separate DES? The timing should not be an issue based on the bandwidth capabilities of the devices. Can you also provide for me a block diagram of your setup as well as an image of the water ripple effect. 

Best,

Zain A

Hi:
We use a separate screen, a DS90UB948 inside the 12.9-inch screen, and a DS90UB948 inside the 15-inch screen.
These two are independent.
Make our block diagram as follows






The following is a picture showing abnormal screen with water ripples and serrated shapes:

Hi,

Can you try running des Only PATGEN and SER only PATGEN when you generate the script so we can deduced where the issue is coming from. There are toggles in the UserConfig of scriptGen that will allow you to do this and see if you are still experiencing the same issues. If DES-only PATGEN shows the issue, it'd point to somewhere between the DES output and TCON input. Is this artifact consistent with another set of displays as well? 

Best,

Zain A

12.9 panel：
Whether it is the serial display pattern screen or the deserial display pattern screen, there is no abnormality showing water ripples in the 12.9 panel display.

15 panel：

The verification situation is as follows: Using the deserial to display the pattern has not taken effect, and it is suspected that it is related to TCON's restriction of access to 948. Using the serial to display pattern is bleow.

Hi,

Could you provide to me the Mode straps that the 948 is on to see what output mode you have it set on. Specifically MODE_SEL0 which controls if the odd and even output channels can be swapped.

Best,

Zain A

Hello Zain：

We are also consulting the screen supplier for information related to 948 deserializer. We cannot confirm the MODE_SEL configuration at present. You can analyze it first from the 948 register dumped in the attachment above.
Also, please tell me if the 15-inch screen is a Sync Mode screen and the 12.9-inch screen is a DE Mode screen. Whether the serializer 941 only supports DE mode screens when using external ref clk can only be displayed normally.

Hello,

Reg 0x49 which contains the FPD_TX Mode, and currently it is set to 0x00 from your register dumps meaning it is on 00 : Dual FPD/OLDI output, so can you try writing 0x81 which would change it to the Dual SWAP FPD/OLDI output:

board.WriteI2C(desAddr, 0x49, 0x81)

board.WriteI2C(desAddr,0x1,0x1)

This is for the 15 in panel 948 DES and let me know if any changes occur.

Best,

Zain A.

Hello Zain：

I have tried writing to the 15-inch screen 948 register configuration and reset, but nothing happened. The read value is still the previous value of 0. 





Judging from the values of 948 registers 0x3 and 0x6, the registers of the 15-inch screen 948 are locked and cannot be controlled through I2C pass through. 

Hello TI

The following is the interface connected to the 948 deserializer chip through the USB2ANY tool
 

When I perform the following configuration, the display effect is a little blurry than before, but when read, the value is 0x01, not 0x81

board.WriteI2C(desAddr, 0x49, 0x81)

board.WriteI2C(desAddr,0x1,0x1)

hello 

Is there any registers for DS90UB941 that can read the timing and porch value, i want to check if DS90UB941's porch is the same with soc config.

Hi,

You can do a resolution dump with the 948 with this script here, but this only provides the Hactive and the Vactive pixels

import time
UB948 = 0x58
time.sleep(1)
board.WriteI2C(UB948,0x68,0x19) # H active High monitor
Hhigh = board.ReadI2C(UB948, 0x69, 1)
board.WriteI2C(UB948,0x68,0x09) # H active Low monitor
Hlow = board.ReadI2C(UB948, 0x69, 1)
board.WriteI2C(UB948,0x68,0x39) # V active High monitor
Vhigh = board.ReadI2C(UB948, 0x69, 1)
board.WriteI2C(UB948,0x68,0x29) # V active Low monitor
Vlow = board.ReadI2C(UB948, 0x69, 1)
mask = int('00111111',2)
hlowmask = Hlow & mask
hhighmask = Hhigh & mask
vlowmask = Vlow & mask
vhighmask = Vhigh & mask
hhighmask = hhighmask << 6
vhighmask = vhighmask << 6
Hactive = hhighmask | hlowmask
Vactive = vhighmask | vlowmask
print Hactive ,"x", Vactive  #print out detected Dimensions

You can also read the porch value pixels of PATGEN through these indirect registers: 

Best,

Zain A.

Hello

Use 948 to type patgen and run the script for the correct screen resolution.

Because 941 and 948 currently do not have direct registers for outputting porch, only use the patgen screen to read the relevant registers to obtain whether the screen parameters have changed. It has been proved that the porch configuration of the patgen register is read in 941 and 948, and no exception is seen.

This is the verification I am currently doing. Today I tried to use the 941 internal ref clk verification Internal Reference Clock Mode. Can you give me some debugging suggestions?

Hi, 

Just to confirm you are still getting the same blurry effects with PATGEN enabled as well? And when you use the internal divided clock you do not get any issues, only when you utilize the external pixel clock?

Best,

Zain A

This is not the case.
When using internal timing, there is no water ripple, whether it is the external dsi clock or the ref clock.

When using external timing, only the dsi clock is normal, and there will be water ripple when using the reference clock.
Do you have any solutions to this problem?

Hi,

In External Reference Clock mode it is recommended that the REFCLK frequency is matched to the DSI PCLK frequency, please refer to this DSI bring up guide:

 https://www.ti.com/lit/an/snla356/snla356.pdf?ts=1753394222325&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FDS90UB941AS-Q1

Also ensure that the reference clock frequency stability is in the recommended rage as listed in the datasheet. Also are you using a Spread-spectrum reference clock? If so the spread percentage needs to also be within spec.

Best,

Zain A

1. I found the hardware to confirm that this reference clock meets the requirements, and I also turned on SSC to try to spread the frequency, but it was not effective. You don’t quite understand what the box is, what does ppm mean?

2. I took a clearer pixel picture with my mobile phone, as shown in the figure below, like the screen parameter porch value given by the SOC configuration is the same as the screen output on the screen. Or is it because of the internal synchronization mechanism of 941, the screen is a sync mode screen. Do you know which parameter has exceptions in hfp, hbp, hsw？

Hi,

PPM stands for parts per million, and it indicates how much your crystal's frequency may deviate from the nominal value. So oscillators and other frequency control devices specify their frequency variation in units of parts per million. df = variation in Hz would be:

?? ? said:

When using external timing, only the dsi clock is normal, and there will be water ripple when using the reference clock.
Do you have any solutions to this problem?

Could you also clarify here? So when utilizing the external timing and reference clock, the 12.9 in screen is still okay correct? Only the 15in panel has the issue in this case?

Best,

Zain A

Yes, only 15in panel has the issue. The effect of adjusting the hfp and hbp porch is this, so it is still suspected that the external clock and timing synchronization mechanism of 941 are caused.  
Because 941 does not have a register that controls timing internally, only the patgen register can control timing, so there is no problem using internal timing.

Hi,

If the same setup works fine with the 12.9 in, then it could be that the blanking pixels timing of the 15 in could be incorrect, are you sure of this timing?

?? ? said:

The 15 panel external timing is below:

119 static struct dsi_panel_param dsi_panel_parameter[] = {
120 //15inch
121 {
122 .t_clk_post = 0x0e,
123 .t_clk_pre = 0x1e,
124 .h_active = 2240,
125 .v_active = 1260,
126 .h_front_porch = 24,
127 .h_back_porch = 40,
128 .h_sync_width = 28,
129 .v_front_porch = 6,
130 .v_back_porch = 4,
131 .v_sync_width = 2,
132 },

Also, which version of scriptGen are you utilizing? can you send me your userConfig file?

Best,

Zain A

I'm not sure if the 15-inch screen parameter can be lit on the 12.9-inch screen, I'll try to confirm. It is normal to confirm that the 15-inch screen parameter has been confirmed, otherwise it is impossible to use the soc dsi clk without any problem.

scriptGen is not generated, we cannot generate 941 scripts, the content we wrote ourselves is as follows:

board.WriteI2C(0x34, 0x01, 0x08); # Disable DSI

board.WriteI2C(0x34, 0x40, 0x04); # Select DSI Port 0 digital registers
board.WriteI2C(0x34, 0x41, 0x05); 
board.WriteI2C(0x34, 0x42, 0x3c); # DPHY_SKIP_TIMING
board.WriteI2C(0x34, 0x41, 0x21); # DSI_CONFIG_1
board.WriteI2C(0x34, 0x42, 0x60); # Set DSI_VS_POLARITY=DSI_HS_POLARITY=1
board.WriteI2C(0x34, 0x5b, 0x03); # Force Dual FPD-Link III Transmitter mode
board.WriteI2C(0x34, 0x4f, 0x8c); # Set DSI_CONTINUOUS_CLOCK, single DSI, 4 lanes, DSI Port 0 input
board.WriteI2C(0x34, 0x03, 0x9A);

board.WriteI2C(0x34, 0x1E,0x01); #Selects Port 0

board.WriteI2C(0x34, 0x66,0x04);

board.WriteI2C(0x34, 0x67,0x1c);#Total Horizontal Width: 0~7

board.WriteI2C(0x34, 0x66,0x05);

board.WriteI2C(0x34, 0x67,0x09|(0x08<<4));#Total Horizontal Width: 11~8 |Total Vertical Width:3~0|

board.WriteI2C(0x34, 0x66,0x06);

board.WriteI2C(0x34, 0x67,0x4F);#Total Vertical Width: 11~4

board.WriteI2C(0x34, 0x66,0x07);

board.WriteI2C(0x34, 0x67,0xC0);#Active Horizontal Width: 0~7

board.WriteI2C(0x34, 0x66,0x08);

board.WriteI2C(0x34, 0x67,0x08|(0x0C<<4));#Active Horizontal Width: 11~8 |Active Vertical Width:3~0|

board.WriteI2C(0x34, 0x66,0x09);

board.WriteI2C(0x34, 0x67,0x4E);#Active Vertical Width: 11~4

board.WriteI2C(0x34, 0x66,0x0A);

board.WriteI2C(0x34, 0x67,0x1c);#Horizontal Sync Width:

board.WriteI2C(0x34, 0x66,0x0B);

board.WriteI2C(0x34, 0x67,0x02);#Vertical Sync Width:

board.WriteI2C(0x34, 0x66,0x0C);

board.WriteI2C(0x34, 0x67,0x28);#Horizontal Back Porch Width

board.WriteI2C(0x34, 0x66,0x0D);

board.WriteI2C(0x34, 0x67,0x04);#Vertical Back Porch Width

#Set Sync Polarities

board.WriteI2C(0x34, 0x66,0x0E);

board.WriteI2C(0x34, 0x67,1<<1|1<<0);

board.WriteI2C(0x34, 0x66,0x0F);

board.WriteI2C(0x34, 0x67,60);

board.WriteI2C(0x34, 0x66,0x03);

board.WriteI2C(0x34, 0x67,8);

board.WriteI2C(0x34, 0x66,0x1A);

board.WriteI2C(0x34, 0x67,2);

board.WriteI2C(0x34, 0x56, 0x01); # Use External reference clock

board.WriteI2C(0x34, 0x65, 1<<3);

board.WriteI2C(0x34, 0x64, 1<<0|1<<2);

board.WriteI2C(0x34, 0x01, 0x00); # Enable DSI

Hi,

Can you allow 1-2 business days and I'll get back to you.

Best,

Zain A