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LMK05318B: monitoring PLL1 lock

Part Number: LMK05318B


Tool/software:

Hi Community

I am currently making some experiments with the EVM Kit and have some questions about the STATUS flags.

My setup  is configured as follow : PRIREF=10MHz ; XO=32.768 MHZ ; DPLL used with 30 Hz bandwidth ; PLL2 unused.

I am also using the LEds indicators to monitor status flags in real time. (R48 register making the selection). specially PLL1 behaviour

  • What is the PLL1 Digital lock detect (mentionned in the datasheet but without explanation) compared to APLL1_lock_detect ?
    • For example selecting "PLL1 DLD makes" the status led to bright , while selecting "APLL1_lock_detect" switches OFF the LED

  • When selecting "APLL1_lock_detect" the led is always OFF independently of  PRIREF being active or not .
  • idem for PLL1 DLD which is always ON

with best regards,

Bruno

  • I believe that the APLL will stay locked when PRIREF isn't active if the DPLL is in HOLDOVER mode.  You can tell by looking at register 14 bit 4.

    I've had better luck routing "DPLL Phase Lock Detected (LOPL#)" and "DPLL Loss of Lock (LOFL)" to STATUS0 and STATUS1 respectively.  You have to set STAT0_POL to 1 and STAT1_POL to 0,  That should make the LEDs light when there's a loss of DPLL phase lock and frequency lock.

  • Hi Bruno,

    Sorry for the delay, I didn't hit "Reply".
    We are going to reduce an update programming manual very soon (likely next week).

    The LOL_APLL1 is not recommended for monitor APLL1 lock. We're removing it as an option due to confusion. Instead, you should use the PLL1_DLD flag as you've found. The PLL1_DLD is a "coarse" detector that gets set when the PLL1 tuning voltage is within the expected threshold necessary for PLL lock.

    As George mentioned, if you are using the DPLL, the LOPL and LOFL flags are better to use because they are "fine" detectors that monitor the frequency and phase instead of the tuning voltage range.

    Regards,

    Jennifer