LMX2572LP: PLL lock after SYNC

Part Number: LMX2572LP

Tool/software:

Hello,

I have two LMX2572LP in my design and they work fine with VCO_PHASE_SYNC=1, and produce the correct frequencies.

After pulsing the SYNC pulse, we wait for each of these PLLs to lock, by checking the MUXout pin for lock detect for both.

Question1: is this an acceptable method, to check the MUXout lock detect pin? We do see this seems to work, but wanted to confirm.

After an interval we do see this pin go high. Also confirmed that by changing MASH_RST_COUNT we can adjust the delay.

Question2: are both PLL's MUXout (lock detect pin) expected to go high simultaneously at exactly the point when phase sync has occured, or perhaps a fixed delay after phase sync has occurred?

Or can the two MUXout lock detect pins go high at different times?

This will help us determine if phase sync has actually occurred or not.



Thanks,

Arun

  • Hi Arun,

    A SYNC pulse will trigger a VCO calibration and synchronization. 

    PLL lock and synchronization are two different things, the PLL can be locked but not synchronous. There is no way for the individual device to know if synchronization is successful. Measuring the phases from these devices is the only way to know if they are synchronized. 

  • Hello Noel,

    I had marked the question closed as you had replied to my question perfectly.

    I have a new related doubt: if I have two LMX2572LP which I am trying to get into phase sync using the SYNC pulse, will the phase sync be expected to happen in the same amount of time each time for a particular frequency setting?
    Or is it as you said: the only way to know when phase sync occurred is to measure the phases?

    Thanks,

    Arun

  • Hi Arun,

    Synchronization will stop after MASH_RST_COUNT is time out, we should configure this register with sufficient time to ensure synchronization can be complete before the counter is time out.