Other Parts Discussed in Thread: LMK05028, LMK5B12212, LMK5B33414, LMK5B33216
Tool/software:
Hi,
I'm new to working with clocking and timing devices. I’m currently using the LMK05028EVM and trying to configure it so that a output signal(on OUT6) is phase-locked and frequency-locked to a 1 PPS signal connected to REF_IN2 (IN2_P pin).
My goal is to generate a 10 MHz clock output that aligns precisely with the rising edge of the 1 PPS reference.
I have:
- 1 PPS connected to IN2_P
- TCXO on board
- Desired output = 10 MHz on OUT6, phase-aligned to 1 PPS
Could you please guide me on:
1. Proper DPLL configuration for this setup (should I use DPLL1 or DPLL2?)
2. How to enable and correctly configure Zero Delay Mode (ZDM)
3. Recommended settings in 1-PPS Jitter threshold section
Thanks in advance for your support!
I have attached you my configuration file :