LMK04832-SEP: Frequencies Requirement Confirmation

LMK04832-SEP is a phase locked loop that nominally requires a reference oscillator input, as opposed to an XO or equivalent which appears to be what you want. At this time, TI does not have any space-grade oscillators, we only have PLLs which require some reference oscillator input.

Additionally, LMK04832-SEP has one common clock distribution path frequency, which is the source to all output dividers, and all output dividers are integer divide only. The least common multiple of the required outputs is 59.4GHz. The maximum supported clock distribution path frequency is 3.255GHz. There is no configuration of LMK04832-SEP which can simultaneously support all the required output frequencies. The minimum number of LMK04832-SEP required for the frequencies requested is two: one can generate 200MHz, 24MHz, and 25MHz from a 3GHz VCO, and the other can generate 148.5MHz from 2970MHz (divide-by-20 - there are other options but this one gives the best choice of reference frequencies). At least one reference oscillator input would be required as well, but it could be something standard like 10MHz or 100MHz. This reference could be cascaded from OSCin to OSCout of the first device, into OSCin of the second device, such that the application only requires one reference oscillator to generate all four frequencies.

Hi Dinesh,

Change the output format in clock outputs flex page.

Pl3aaee note not all outputs support LVCMOS output.

best regards,

vicente

Hi Vicente,

Thank you for the information. 

Regards,
Dinesh

Hi Dinesh, 
PLL2 isn't locked as N/R value * PFD ! = VCO frequency (3GHz) 

There is a mathematical relationship between the VCO, and effecticely the PFD in this case. 

In your case, you have a 122.88MHz PFD frequency the total N divider (taking into account the prescaler) is 24. 

122.88MHz * 24 = 2949.12MHz 

Please upload a clock tree of what your input clock is and desired outputs. 

I see you uploaded this but in case somethings changed please include in your clock tree. 

As Derek mentioned, this frequency plan specifically cannot be generated by the LMK04832-SP as the VCO coverage is limited from 2440MHz to 3255MHz. 
Ensure the LCM of the outputs frequency you need falls under the VCO coverage range of the LMK04832-SP.

Best regards, 

Vicente 

Hi Dinseh, 
What is your ref clk, is this a VCXO, XO, etc? 
Do you plan on jitter cleaning or is your ref clk clean and you only want to operate in single loop (PLL2 only) mode which effectively acts as a clock generator? 

I have created a config that assumes a 100MHz input with LMK04832 operating in single loop mode . 100MHzIn_SingleLoop_200_100_25_24MHzOut.tcs

Best regards, 

Vicente 

Hi Vicente,

Thank you for the information.

Regards,
Dinesh