CDCS503: About the start-up sequence

Ryu,

How many boards is this on relative to the total number of boards?

How are the control pins configured when this behavior occurs?

Thanks,

Kadeem

Hi Kadeem,

This occurred on only one of the 30 evaluation boards.
OE, FS, SSCSEL0, and SSCSEL1 are connected to VDD (3.3V), so they rise simultaneously and then the clock is input.

Best Regards,
Ryu.

Yamashita-san,

If these pins are all left floating externally (pulled high through internal pull-ups), does the issue persist?

Thanks,
Kadeem

Hi Kadeem,

It goes away when I turn the power back on, and the phenomenon may or may not reproduce, so I cannot test the operation by internal pull-up.
I have 12.5MHz input and set it to 50MHz, but sometimes the frequency is about 1.33 to 1.5 times higher.
Is there any chance of this kind of bug?
If so, what are the possible causes?

Best Regards,
Ryu.

Yamashita-san,

I have not heard of this issue being reported before.

If you do an ABA swap (swap the device with one on a known-good board), does the issue follow the board or follow the device?

Thanks,

Kadeem

Hi Kadeem,

It is difficult to confirm with ABA swap because it does not occur every time.
This is a one-point confirmation.
I am inputting PLL from FPGA to this device, but the input starts before the PLL is stable.
Even if it stabilizes, the same symptom occurs.
Is there any possibility that this could be the cause?

Best Regards,
Ryu.

Hi Kadeem,

In other words, as long as VDD is input, any output from any PLL is acceptable?

Also, the recommended circuit diagram in the following application note has an LC filter for 3.3V, but this is not essential, is it?

https://www.ti.com/jp/lit/an/scaa103/scaa103.pdf

Best Regards,
Ryu.