Tool/software:
Hi,
This is Dinesh from iWave Global. I have a doubt regarding the use of LMK04832 clock file in LMK04368 Clock Synthesizer. Please confirm this if we can use.
If I provide 3000MHz in VCO1, the PLL2 is not locked. Is there any issue because of this? Please check and confirm. Attached the screenshot for reference. Looking forward to the response.
Regards,
Dinesh
Hi Dinesh,
PLL2 is not locked.
The there is a mathematical relation ship that needs to be followed for PLL to lock.
In order to generate a 3GHz VCO from a 122.88 MHz reference only the following N/R combination meets this:
Please note this combination due to very low PFD freq (0.96MHz) and large divider values will suffer from poorer phase noise performance.
I suggest instead of a 122.88MHz VCXO, use a 100MHz VCXO as this will reduce the N dividers and increase the PFD by a good amount providing much better phase noise.
For example:
Please note you can also use the frequency planner
Best regards,
Vicente
