Tool/software:
Hello!
What is the recommended way to handle the PWRGD signal if the PWRDN functionality is not used?
The datasheet states the following:
"The first low-to-high transition of the PWRGD pin after device power is on can occur while input clock is running, floating, low/low or pulled to VDD. The power-up sequence only starts if the PWRGD pin is pulled from low to high while input clock is valid.
If the PWRGD pin is pulled from low to high while input clock is invalid, then the power-up sequence is not initiated and the outputs stay low/low. When this happens, pulling the PWRGD pin back from high to low has no impact and this low-to-high transition on PWRGD pin is not considered a valid Power Good signal. The device is powered up next time when the PWRGD pin is pulled high while input clock is valid. In other words, there is only one valid Power Good signal for every power cycle."
What would happen if the PWRGD pin is permanently pulled high to VDD and the clock signal became active after VDD/PWRGD? Would the output be enabled when a valid clock is detected, or would another low-to-high transition be needed?
