Tool/software:
Hi,
Please advise me on question bellow
The CDCE913 datasheet states as bellow.
8.3 Power Supply Recommendations
When using an external reference clock, XIN/CLK must be driven before VDD ramps to avoid risk of unstable
output.
If you don’ t follows this note and the device gets into unstable output, can make
the device recovers from such abnormal situation by toggling the Power Dwon bit in
the register or re-write the PLL divider bits in the registers?
Mita
