• State TI Thinks Resolved
  • Replies 4 replies
  • Answers 2 answers
  • Subscribers 23 subscribers
  • Views 131 views
  • Users 0 members are here
Support feedback
Options
Options
Related

CDCLVP111: IBIS model inquiry

KH Hoo
Prodigy 10 points
Part Number: CDCLVP111

Tool/software:

Hello,

I'm using the rev B IBIS model to check my 2.5GHz and 200MHz clock quality. I have put 86ohm of termination to ground following the datasheet. My questions are:

1. Is CDCLVP111 output a pull up open drain driver, hence it needs the 86ohm pull down external termination?

2. If #1 is true, can the 86ohm pull down terminate to higher/lower than VEE without causing reliability and back power issue? What is the allowable range of the termination rail for 2.5V-3.8V configuration?

3. Is it expected to have imbalance swing, e.g. the differential cross point to max vs. differential cross point to min has significant delta?

Thanks. 

  • 0
    Intellectual 330 points
    • Yes, the CDCLVP111 features an open-emitter LVPECL output driver (not exactly pull-up open drain, but similar in requiring external biasing as it sources current but does not sink it effectively). This necessitates external termination, such as 86 Ω emitter resistors placed near the driver for proper biasing and signal integrity, as specified in the datasheet for certain configurations (e.g., to match impedance and ensure operation).
    • Yes, the open-emitter structure requires external pull-down termination. Terminating the 86 Ω resistor to a voltage higher or lower than VEE (typically ground, 0 V) is possible but must stay within reliability limits to avoid stress or back-powering. The recommended termination is to VTT = VCC - 2 V (e.g., 0.5 V for VCC = 2.5 V, 1.3 V for VCC = 3.3 V, 1.8 V for VCC = 3.8 V) using 50 Ω resistors or Thevenin equivalent for DC coupling. Terminating to ground (VEE = 0 V) is allowed (as in some datasheet examples) but may increase bias current by 2–3 mA per output pair compared to VCC - 2 V, potentially affecting power dissipation. For the 2.5 V–3.8 V VCC range:
      • Allowable termination rail (VTT): VEE - 0.5 V to VCC + 0.5 V per absolute maximum ratings (to avoid ESD diode conduction or stress), but recommended VEE (0 V) to VCC - 2 V for optimal performance and signal levels.
      • Back-powering risk: If VTT > VCC, current can flow through ESD diodes, powering the device unintentionally and causing reliability issues (e.g., latch-up). If VTT < VEE - 0.5 V, it may stress the outputs. Use VTT ≤ VCC - 2 V to prevent this.
    • No, significant imbalance in differential swing (e.g., large delta between cross-point max and min) is not expected in normal operation or the IBIS model when properly terminated (e.g., 50 Ω to VCC - 2 V). The datasheet specifies a symmetric differential output voltage swing of 600 mV min (terminated 50 Ω to VCC - 2 V), with low output-to-output skew (15 ps typ). Any observed imbalance in your simulation may stem from model limitations (e.g., Rev B IBIS not fully capturing high-frequency behavior at 2.5 GHz), improper termination setup (e.g., to ground shifting common mode), or simulation tool settings (e.g., mismatched trace impedances or noise). Verify by simulating with datasheet-recommended VCC - 2 V termination
  • 0 in reply to SUNILBHAI PATEL
    Prodigy 10 points

    Thanks for confirming #1 & #2. For #3, please see the waveform snapshot below. I was comparing between ground termination vs. 0.5V VTT termination. Both are using LVPCLK_OUT_2V5_slow model without any channel in between a 100nF AC couple to my RX (no channel included to get rid of any potential variable from channel). The termination is an ideal 86ohm to either ground or 0.5V VTT. The top 2 waveforms are the IBIS model output and AC couple to RX input with ground termination, while the bottom 2 waveforms are the IBIS output and AC couple to RX input with 0.5V VTT termination. With ground termination, we are seeing about 130mV delta. For 0.5V VTT termination, it is slightly better but still I'm seeing about 100mV delta. Please confirm if this is aligned with TI design team observation. If Rev B IBIS not fully capturing high-frequency behavior at 2.5GHz, what would be the recommendation to make sure my RX circuitry + channel model works when it is pairing with CDCLVP111? Currently, i'm seeing the asymmetrical swing is causing my RX input common mode to be shifted.

     

  • 0 in reply to KH Hoo
    Prodigy 10 points

    Btw, is the IBIS model including package level trace route and package ball RLC?

  • 0 in reply to KH Hoo
    TI__Mastermind 29272 points

    Hi KH, 
    Yes, IBIS models include parasitic with pin modeling being done from bond wire landing point all the way to package pin. 

    Best regards, 

    Vicente