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LMK04828: PLL1 and PLL2 lock question

Tai Sim Yeoh
Prodigy 45 points
Part Number: LMK04828

Tool/software:

Hello TI Support,
           I have a question in regard to the PLL1 and PLL2 of the LMK04828B IC.

           Per the specifications, PLL1 phase detector frequency is spec-ed to be 40 MHz maximum, while PLL2 phase detector frequency is 155 MHz max.




            However I only managed to configure them to be outside of spec to obtain the PLL locks (i.e. PLL1 & PLL2 phase detectors @ 122.88 MHz and).

            Any  other configuration I do to ensure PLL1 and PLL2 detectors to be within spec causes PLL1 to fail to lock.

            Can I check if there is an error in the datasheet (or I have an older version) that explains the behavior I am seeing?

            Attached are some TIcProSW configuration files that shows both my configuration whereby PLL1, PLL2 locks (refer to "PLL1_PLL2_Locks.tcs") and PLL1 fails to lock (refer to "PLL1 Fail to Lock.tcs").

            I am trying to understand where the discrepancies are or there is something I am missing that explains the behavior I am seeing.

            Any help you can provide is appreciated.

           Thank you.

Regards
TaiPLL1_PLL2_Locks.tcsPLL1 Fail to Lock.tcs



  • 0
    TI__Mastermind 29232 points

    Hi Tai, 
    Currently you have PLL1 PFD to 30.72MHz as well as PLL2 PFD. 

    This config should result in lock. 

    In the case for PLL2, I increased the PFD frequency to 122.88MHz to gain a few db in the PLL region of the output PN. 

    Best regards, 

    Vicente 

    PLL1 Fail to Lock revised.tcs

  • 0 in reply to vicente flores prado
    TI__Mastermind 29232 points

    I don't understand how you would get the above config to lock... 
    Are you using the device EVM or a custom board? 

    Best regards, 

    Vicente 

  • 0 in reply to vicente flores prado
    Prodigy 45 points

    Hello Vicente,
             Thank you for your assistance. I am using a custom design from Abaco (i.e. FMC216).

             Re: How I managed to get the PLL to lock
             This is the mystery I am trying to understand.
              I am not sure how the LMK configuration for an internal PLLL can be impacted by the custom design when TicProSW configuration indicated PFD for PLL1 is out of spec.

              Any other clarification/theory you can provide is appreciated.

    Regards,
    Tai

  • 0 in reply to Tai Sim Yeoh
    TI__Genius 9010 points

    Hi Tai,

    I took this into the lab to try to replicate the issue. Something seems off with your configuration file because even when I used PFD1 values within spec, I did not see PLL1 lock. However, when I used the default configuration in TICS Pro, adjusted the SYSREF settings and outputs (which I would recommend you changing as you see fit), I managed to achieve lock with both PLL1 and PLL2. Some registers may have gotten set inappropriately, but I am not sure how that would have allowed PLL1 to lock at a frequency beyond spec.

    confirmed_locking_4828.tcs

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    Prodigy 45 points

    Hello Michael,
          Thank you for info/help in reproducing the problem.
     
           I am baffled as well how the thing works.

           I will try your suggestion and will update with my results.

    Regards,
    Tai

  • 0 in reply to Tai Sim Yeoh
    Prodigy 45 points

    Hello Michael,
            I managed to try your suggestion and unfortunately it does not work for my set up.

            I tried the two scenarios below, and both failed (the intention of my tests is just to see the PLL1/2 locks statuses):
            a) Used your configuration as-is (with only changes to register 0x15F = 0x3B to allow SPI Readback)
            b) Used your configuration as a base + modifications to fit the clock output configuration for us in my design

            Can I check if there is any external design around the LMK04828B that would affect PLL1 locking?

            Unfortunately I do not have the schematics for the design (i.e. off the shelf part) hence I could not "see" the design around the LMK04828B.

            Any help and suggestion you can provide is appreciated.

    Regards,
    Tai

  • 0 in reply to Tai Sim Yeoh
    TI__Genius 9010 points

    Hi Tai,

    PLL1 could be prevented from locking by a few external design choices. The main factors that would result in PLL1 being unable to lock is the on-board VCXO value being wrong, the dividers being incorrect relating to PFD1, or the loop filter for PLL1 being set incorrectly. 

    The most basic choice for the loop filter (of the 2nd order variety) can be seen in the Pllatinum Sim screen attached.

    Beyond these, incorrect input matching or input path layout issues could result in loss of lock - but given that you are using a pre-designed card, I would not initially suspect these being the contributing issues.

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    Prodigy 45 points

    Hello Michael,
             Thank you for the info. Let me continue with my investigation on my end and will update the thread when I find new info and have any additional question.

             Again I appreciate the quick response from your end.

    Regards,
    Tai