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CDCE72010 external clock reference

Cristiano Rodrigues
Prodigy 125 points
Other Parts Discussed in Thread: CDCE72010



I'm facing a problem to configure this component, it doesn't lock.

The filter values (charge pump output) are:

C1: 100nF
R2: 2k7
C2: 22uF
R3: 160ohms
C3: 100nF


The inital config for  CDCE (with 100MHz internal reference) is:

R (Reference Divider): 1
P (Feedback Divider): 8
M Divider: 625
N Divider: 384
Which takes the PDF freq to be 160kHz, recommended by component datasheet.

However , I need to replace the 100MHz reference by an external 10MHz reference, but can't reach 160kHz in PFD. I found 80kHz with:

R (Reference Divider): 1
P (Feedback Divider): 48
M Divider: 125
N Divider: 128

The PLL doesn't lock in such situation with 80kHz. Is there any other way to configure PLL to solve this problem?

  • 0
    TI__Guru* 81034 points

    Hi Cristiano,

    It looks like the loop filter may not be stable for these settings. Can you tell us the desired loop bandwidth needed for your application and we can recommend the R/C values? Also, can you send the register settings?

    Best regards,

    Matt

  • 0 in reply to Matt Sunna
    Prodigy 125 points

    Hi Matt

    Thanks for your answer.

    The system uses a 491.52MHz VCXO and a 100MHz clock reference (forgot to mention before), I'd like to change the reference to 10MHz.

    The filter bandwidth for the aplication is 1kHz.

    Is there any ready solution (in terms of filter components values) to these frequencies we are working with? We've searched for an AN and couldn't find it.

    Here follows registers values:


    address value
    0       683C039
    1       6800002
    2       6A04000
    3       6800000
    4       E984000
    5       6800000
    6       6800000
    7       8384001
    8       6800009
    9       68050CC
    A       00FC02C
    B       00002C0
    C       0000180

    All values hexadecimal.

    Thanks and regards,

    Cristiano

  • 0 in reply to Cristiano Rodrigues
    TI__Guru* 81034 points

    Hi Cristiano,

    The value of register 10 may have some problems - for the M/N divider values you described, I suggest changing this to 01FC07C. For the loop filter, changing R2 to ~200ohms (instead of 2.7k) should really improve the stability and performance. We use a loop filter simulator http://e2e.ti.com/support/clocks/m/videos__files/212419.aspx to help with these type of simulations and the upcoming GUI release for CDCE72010 will have this simulator integrated.

    I hope this helps,

    Matt

     

  • 0 in reply to Matt Sunna
    Prodigy 125 points

    Hi Matt, thanks again.


    Following your recommendation of replacing resistor R2 from 4k7 to 200ohms lead to a result that concerned me: margin phase became approx. 10 degrees instead of approx 80.

    I checked this by using a TI PLL spreadsheet calculator instead of the simulator you recommended. The simulator crashes even before I finish to fill in data. I tried to run it on Windows XP service pack 2, service pack 3 and Windows 7 but I couldn't figure out why it crashes.

    Then I simulated your changes on the spreadsheet. (I've tried to attach it already configured for our application, but upload crashes). Considering that this filter was originally designed for a PFD frequency of 160kHz and now it became 80kHz, how such a large change on phase margin value will affect PLL performace?