Tool/software:
Hello,
I'm having some difficulties in getting the LMX2594 VCO to lock. I don't know if this has to do with my initial register setup or not. I will describe the method that I'm using to calibrate the VCOs.
How long does the chip takes to run through the calibration? Should query the rb_LD multiple times before reading the VCO_CAPCTRL and VCO_DACISET?
When Register 110 is reporting Unlocked (Vtune Low or Vtune High), how do I get it back into lock? which register should I adjust? Maybe VCO_CAPCTRL and/or VCO_DACISET?
I also want to point out that I don't have access to any of the TI application tools to debug this. I'm simply utilizing SPI interface into the chip.
I've tried to attach a flowchart of my implementation, I'm not sure if I could attach an image here or not. Your help would be greatly appreciated.
Thanks
Sam
For VCO = 1 to 7 VCO_SEL = 7 % Supplier recommends for every internal calibration run VCO_DACISET_STRT = 300 % Supplier recommends for every internal calibration run VCO_CAPCTRL_STRT = 183 % Supplier recommends for every internal calibration run QUICK_RECAL_EN = 1 % Avoided unlock issues around VCO4/5 overlap region if VCO = 1 F_start = 7620 MHz F_step = 6.405228 MHz N_step = 153 PFD_DLY_SEL = 1 CHDIV=12 (decimal 4) if VCO = 2 F_start = 8600 MHz F_step = 7.248321 MHz N_step = 42 PFD_DLY_SEL = 1 CHDIV=12 (decimal 4) if VCO = 3 F_start = 10544 MHz F_step = 6.474819 MHz N_step = 40 PFD_DLY_SEL = 1 CHDIV=12 (decimal 4) if VCO = 4 F_start = 10800 MHz F_step = 8.510678 MHz N_step = 141 PFD_DLY_SEL = 1 CHDIV=6 (decimal 2) IF FVCO_Freq > 11900 MHz and < 12100 MHz VCO_SEL = 4 VCO_CAPCTRL_STRT = 1 QUICK_RECAL_EN = 1 if VCO = 5 F_start = 12000 MHz F_step = 6.081080 MHz N_step = 148 PFD_DLY_SEL = 1 CHDIV=6 (decimal 2) if VCO = 6 F_start = 12900 MHz F_step = 6.666666 MHz N_step = 150 PFD_DLY_SEL = 2 CHDIV=6 (decimal 2) if VCO = 7 F_start = 13900 MHz F_step = 6.346153 MHz N_step = 57 PFD_DLY_SEL = 2 CHDIV=6 (decimal 2) For N = 0 to (N_step-1) FVCO_Freq = Fstart + N*F_step PLL_N = INT(FVCO_Freq/10.1818) if VCO=5 if FVCO_Freq > 12500 MHz PFD_DLY_SEL = 2 DDS_CLK = 375 MHz DDS_Freq = (FVCO_Freq / PLL_N) x 11 DDS Frequency Tuning Word = FTW = (DDS_Freq x 2^32) / DDS_CLK Write FTW into DDS FCAL_EN = 0 FCAL_EN = 1 rb_LD = Read Register 110, bits [10:9] rb_VCO = Read Register 110, bits [7:5] rb_VCO_CAP = Read Register 111, bits [7:0] rb_VCO_DAC = Read Register 112, bits (8:0] Append all 4 reads into growing file Next N Next VCO
