LMK04828: difference in functionality between SYNC pin and CLKin0 input. Resetting PLL dividers

Tool/software:

From LMK04828 datasheet I know that SYNC pin and CLKin0 pin both go to the same SYNC/SYSREF path

this path can reset SYSREF and CLKout dividers as one can see on the scheme above. 

But from "Multi-Clock Synchronization" I can get information that one can acheive 0-delay not only with PLL setups with integer N/R but also in fractional cases, if resets N and R dividers on parallel clock devices. 

So I am curious if SYNC pin has some functionality, CLKin0 input does not have. Like reseting R and N dividers, for example.