TPL5110: Verification of DRV operation at power-on

Part Number: TPL5110

Tool/software:

Hi

We are considering the TPL5110 for an application where we need a single rising edge x seconds after power on (x can be ~10 or up to 300 seconds).  The TPL5110 seems ideal, but we are not using it as intended to drive a MOSFET.  We are simply needing a single rising edge after power on.  We would have up to 5 TPL5110 chips on our board providing various time-gated functionality. Programmable logic (micro/FPGA)  is not an option. We use these rising edges to latch flip-flops to enforce safety-critical timings. Figure 7-3 in the datasheet shows that in one-shot mode, DRV is shown to stay high during POR and resistance reading.  Is this behavior guaranteed by design?  Should/could we add a weak pull-up on DRV (we are hesitant to do so, as the TPL5110 will be off for quite a while after the board is powered and before we turn on the TPL5110). To be clear, our desire is not to have to toggle any pins on the TPL5110.  We won't use DONE and EN/ONE_SHOT will be tied to GND.  We wish to apply power, and some time later receive a single rising edge.

Thanks
Dave 

  • Hi Dave,

    Once Vcc is applied to the device, DRV pin will turn HIGH until resistance reading is completed. This is how the device is design. 

    Both EN/ONE_SHOT and DONE pin should be tied LOW. 

    DRV is a push-pull output, external pull up is not required. This pin expects a high impedance load that does not virtually draw current.