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LMK05318B: HCSL output to clock buffer

Kartik Vashisht
Intellectual 1735 points
Part Number: LMK05318B


Tool/software:

Hi,
I want to understand if we are connecting HCSL output clock of LMK05318B to 1.8V input buffer devices and provide 3.3V to VDDO of the LMK05318B device, is it okay to DC couple the LMK output to 1.8V input clock buffer?
My understanding is that HCSL output has a swing from 150mV to 880mV (according to datasheet) so DC coupling would mean I have to have a buffer with enough VIH?
There is an internal LDO in LMK for these output buffer, please help to understand what supply these differential clocks are referring to (are they referred to VDDO of 3.3V or 1.8V of LDO) and will HCSL output depend on this reference?

  • 0
    TI__Genius 16895 points

    Hi Kartik,

    Are you buffering to a 1.8V LVCMOS buffer?

    Can you please share the full spec table of the 1.8V input buffer? I can help further confirm. In general, yes, as long as the buffer supports the max/min VOH and VOL levels of the LMK05318B HCSL output, then it is OK.

    For VDDO voltage, the differential swing remains the same (within range per datasheet spec). If the output is configured as LVCMOS, then the VDDO voltage does matter. See note (3) of 7.3 Recommended Operating Conditions section in the datasheet.


    Regards,

    Jennifer