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CDCE6214-Q1: CDCE6214

George Vigelette
Prodigy 10 points
Part Number: CDCE6214-Q1
Other Parts Discussed in Thread: CDCE6214

Tool/software:

Hi Forum,

Above I have our current implementation of the clock IC.  We are getting the correct output frequencies but the output is inverted or 180 degrees out of phase.  We are using OUT3 to drive the next boards clock chip,  Below is the Refrence clock (Yellow signal) from the first board and the OUT3 (blue signal) going to the pri reference input on the next board. 

 Zero delay mode is enabled and below is the register settings.

  

Fullscreen 8880.HexRegisterValues.txt Download 
R85	0x00550000
R84	0x00540000
R83	0x0053FF00
R82	0x005205C0
R81	0x00510004
R80	0x00500000
R79	0x004F0008
R78	0x004E1000
R77	0x004D0000
R76	0x004C0188
R75	0x004B4008
R74	0x004AA181
R73	0x00490000
R72	0x00480027
R71	0x00470006
R70	0x00460808
R69	0x0045A181
R68	0x00440000
R67	0x0043C001
R66	0x00420006
R65	0x00410808
R64	0x0040A181
R63	0x003F0000
R62	0x003EC001
R61	0x003D0000
R60	0x003C0008
R59	0x003B2008
R58	0x003A502C
R57	0x00390000
R56	0x00380027
R55	0x0037001E
R54	0x00363400
R53	0x00350069
R52	0x00345000
R51	0x003340C0
R50	0x003201C0
R49	0x00310013
R48	0x00301A14
R47	0x002F0A50
R46	0x002E0000
R45	0x002D4F80
R44	0x002C0318
R43	0x002B0051
R42	0x002A0002
R41	0x00290000
R40	0x00280000
R39	0x00270000
R38	0x00260000
R37	0x00250000
R36	0x00240000
R35	0x002327F8
R34	0x00220000
R33	0x00212710
R32	0x00200000
R31	0x001F0000
R30	0x001E0249
R29	0x001D0000
R28	0x001C0000
R27	0x001B0005
R26	0x001A0000
R25	0x00193400
R24	0x00180719
R23	0x00170406
R22	0x001600A2
R21	0x00150585
R20	0x00140000
R19	0x00130000
R18	0x00120000
R17	0x001126C4
R16	0x0010921F
R15	0x000FA037
R14	0x000E0000
R13	0x000D0000
R12	0x000C7002
R11	0x000B0000
R10	0x000A0000
R9	0x00090000
R8	0x00080001
R7	0x00070C0F
R6	0x000619EC
R5	0x00050008
R4	0x00040000
R3	0x00030000
R2	0x00020003
R1	0x00012310
R0	0x00001500

we need to get the input 2 MHz signal input and the output to be in phase.  Is there a way to do this?

Thank You,

George Vigelette

  • 0
    TI__Mastermind 22570 points

    George,

    Do you still see this issue when setting the reference doubler to 1 (R25[7:0] = 1) and doubling pll_ndiv to 1170 (R30[14:0])?

    Thanks,

    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 10 points

    I changed the following register writes:

    0x001E1170,

    0x00193401,

    I get the same results, I am triggering on the reference clock rising edge and the out3 is on the falling edge as seen in the original scope capture.

    Thank You,

    George

  • 0 in reply to George Vigelette
    TI__Mastermind 22570 points

    George,

    Try switching to the internal zero delay mode path instead (R0[10] = 1) and recalibrating the PLL. 

    After this, does the device have the correct behavior?

    Thanks,

    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 10 points

    so below is my write function and if I add teh calibrate line in, i get no ouput.  If i remove it i do get output the lock status is never set either way.  The register array is also provided.  We are using a 2MHz input reference clock generating 2MHz output clocks on OUT0, OUT2, OUT3 and 10MHz on OUT1 and OUT4.  Even though when I don't do a recal and it does not lock I do get the 2MHz and 10MHz signals.

    config_CDCE6214_10MHZ_ZDM.h

    static bool ConfigureClock()

    {

    int count = 0;

    uint16_t v = 0;

    // reset

    HAL_GPIO_WritePin(PDN_GPIO_Port, PDN_Pin, GPIO_PIN_RESET);

    HAL_Delay(250);

    HAL_GPIO_WritePin(PDN_GPIO_Port, PDN_Pin, GPIO_PIN_SET);

    HAL_Delay(25);

    //I2C_write_CDCE6214_reg(0x67, 0x000F, 0x5020); // unlock eeprom

    HAL_Delay(25);

    // printf("Configuring Clock chip\r\n");

    // Calculate the number of elements in the array

    // blur6214_64mhz_values

    size_t num_elements = sizeof(cdce6214_v6_10mhz_values) / sizeof(uint32_t);

    // Iterate through the array and split each uint32_t value into two uint16_t values

    for (size_t i = 0; i < num_elements; i++)

    {

    uint32_t value = cdce6214_v6_10mhz_values[i];

    // Split the value into upper and lower words

    uint16_t reg_addr = (uint16_t)(value >> 16); // Upper word is reg_addr

    uint16_t reg_value = (uint16_t)value; // Lower word is reg_value

    // Print the split values

    if (!I2C_write_CDCE6214_reg(0x67, reg_addr, reg_value))

    {

    // printf("failed Index %zu: reg_addr = 0x%04X, reg_value = 0x%04X\r\n", i, reg_addr, reg_value);

    return false;

    }

    HAL_Delay(1);

    }

    HAL_Delay(50);

    I2C_write_CDCE6214_reg(0x67, 0x0000, 0x1510); // calibrate

    for(count = 0; count < 5; count ++){ // check for lock

    HAL_Delay(50);

    v = I2C_read_CDCE6214_reg(0x67, 0x0007);

    if ((v & 0x01) == 0x01) {

    HAL_GPIO_WritePin(SYSTEM_RDY_GPIO_Port, SYSTEM_RDY_Pin, GPIO_PIN_RESET);

    break;

    }

    }

    return true;

    }

    Thank You,

    George

  • 0 in reply to George Vigelette
    TI__Mastermind 22570 points

    George,

    I believe that I see the issue here. I load your settings into TICS Pro and see the following:

    The zero-delay mode is specifically for clocks that come from the PLL. When using REFCLK as the clock source, the clocks are not in zero-delay mode. The clock source for zero-delay must be from PSA or PSB.

    I also recommend increasing the PLL lock detect window from 1.36ns to 8.9ns for improved PLL locking, and change the PLL order from Fractional Order 1 to Integer.

    Thanks,

    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 10 points

    Hi Kadeem,

    Thank you for the information, I did update the feedback to us psa and increased the lock detect window time to 8.9ns and the system does lock now.  Below is the register values being used.  Now this does lock but if i power cycle it locks in different phases and never aligned to the reference clock.  The scope shots show the reference clock and blue is the OUT2 frequency.

    const uint32_t cdce6214_v6_10mhz_values[] = {

    0x00550000,

    0x00540000,

    0x0053FF00,

    0x005205C0,

    0x00510004,

    0x00500000,

    0x004F0008,

    0x004E1000,

    0x004D0000,

    0x004C0188,

    0x004B4008,

    0x004AA181,

    0x00490000,

    0x00480027,

    0x00470006,

    0x00460808,

    0x0045A181,

    0x00440000,

    0x004300C3,

    0x00420006,

    0x00410808,

    0x0040A181,

    0x003F0000,

    0x003E00C3,

    0x003D0000,

    0x003C0008,

    0x003B2008,

    0x003A502C,

    0x00390000,

    0x00380027,

    0x0037001E,

    0x00363400,

    0x00350069,

    0x00345000,

    0x003340C0,

    0x003207C0,

    0x00310013,

    0x00301A14,

    0x002F0A50,

    0x002E0000,

    0x002D4F80,

    0x002C0318,

    0x002B0051,

    0x002A0002,

    0x00290000,

    0x00280000,

    0x00270000,

    0x00260000,

    0x00250000,

    0x00240000,

    0x002327F8,

    0x00220000,

    0x00212710,

    0x00200000,

    0x001F0000,

    0x001E0249,

    0x001D0000,

    0x001C0000,

    0x001B0004,

    0x001A0000,

    0x00190400,

    0x00180719,

    0x00170406,

    0x001600A2,

    0x00150585,

    0x00140000,

    0x00130000,

    0x00120000,

    0x001126C4,

    0x0010921F,

    0x000FA037,

    0x000E0000,

    0x000D0000,

    0x000C7002,

    0x000B0000,

    0x000A0000,

    0x00090000,

    0x00080001,

    0x00070C0F,

    0x000619EC,

    0x00050008,

    0x00040000,

    0x00030000,

    0x00020003,

    0x00012310,

    0x00001500

    };

  • 0 in reply to George Vigelette
    Prodigy 10 points

    here is my config in the tool 

  • 0 in reply to George Vigelette
    TI__Mastermind 22570 points

    George,

    Please change from using the doubler (change the "Doubler/Divide" block from x2 to /1), and double the integer divider (585 to 1170). Does it consistently lock in phase when this is done?

    Thanks,

    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 10 points

    making those changes seem to have the same result.  the clock ic datasheet specifies the reference clock to be 10-200 MHz can that be the issue we are using 2 MHz reference?

    -- George