STARTERWARE-SITARA: AM62x McASP Support for 64MHz Bit Clock and Multiple I2S Data Lines

Hello Venkatesulu,

It is a hardware limitation of the McASP peripheral to have a max of 50MHz frequency, and therefore cannot be extended. Refer to Table 7-72 MCASP Timing Requirements of the AM62x Datasheet for more information. 

For the eight I2S data lines, could you please provide a block diagram to further understand the clock controller/targets?  From a serializer perspective, McASP2 has AXR0...AXR15 and is capable of this. 

Regarding the SDK Driver, DMA and interrupt modes are supported, as well as multi-serializer and multi-slot TDM. Refer to MCASP section of AM62x MCU+ SDK 11.01.00 for more information and key careabouts.

Regards,
Karam

Hello Karam,

Thank you for your quick response.

Please find attached the McASP and Tuner interface connection details. Each McASP is connected with four data lines. McASP1 and McASP2 are primarily used for the Tuner interface.

We plan to utilize 4 AXR pins for each McASP, and I assume the RX buffer along with DMA will be able to handle data transfers at 33 MHz for both the McASPs.

Let me know if you need any further details or clarification.

Regards,

Venkat

Hello Venkat,

Thank you for the block diagram. I have a few points: 

• Are you using an external clock for the 44.1 kHz? If so, there is no concern. Otherwise, we are unable to internally generate that frequency.
  
  
• The block diagram is a little unclear about which device controller/target since it appears that the McASP is receiving the clock given the direction of the arrows, but the McASP is labeled "Master" in the block diagram.
  • From my understanding of the block diagram, the McASP is receiving the clock so the McASP would be the target in this case. If that is correct, then the setup is good.
  • However, if McASP is intended to be the controller, then keep in mind AM62x cannot internally generate the 33MHz audio clock frequency. 

Regards,
Karam

Hello Karam,

There was a typo in the previous attachement the McASP configuration at 33 MHz. To clarify:

• There are two distinct I2S interfaces:
  • Audio Interface (44.1 kHz): McASP0 operates as Master for clocks, and IC1 is the Slave.
  • Radio Interface (33 MHz): McASP1 and 2 operates as Slave, and IC1/2 are the Masters for clocks.

Regarding the Radio interface at 33 MHz, we assume that:

• McASP in Slave mode can support 4 or 8 data lines at this frequency.
• The RX buffer and DMA are capable of handling data transfers at 33 MHz for 4 or 8 lines for both McASP instances simultaneously.

Please let me know if further clarification is needed.

Regards,

Venkat

Hello Venkat,

Where is the 44.1 kHz frequency generated from? We cannot generate that clock internally, and it would require an external reference clock. Otherwise, the system appears to be good.

Please let me know if this helps.

Regards,
Karam