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LMK04828: LMK04828 Clock Input mode Clarification

Part Number: LMK04828

Tool/software:

Hello,

Based on our application, we want to send SYSREF as a pulsed and continuous signal via CLKIN1.
The issue is:
We are using an external LMK in that SDCLK output as LVPECL (differential) and then converting it into a single-ended feed-through clock to another LMK as input, which is single-ended in that CLKIN0 input. We set it as MOS mode. As per the above image, this is a bipolar signal, but still LMK is detecting it. Can you explain how the MOS input works.

  • Hi Thanujashree,

    Let me inquire with a device expert, and I will get back to you.

    Thanks,

    Michael

  • Hi Thanujashree,

    Here is what the expert had to say:

    The MOS input has a differential MOSFET CML structure and larger hysteresis levels, so it works better for DC-coupled applications. LOS is only available when the input is in MOS mode.

    Regardless of whether the device is in Bipolar or MOS mode, the input is AC-coupled internally, and the differing amplifiers is mostly about internal bias and hysteresis levels and making certain features (like LOS) work correctly.

    Thanks,

    Michael

  • Hello Michael Srinivasan,

    Thank you for the Response

    But My doubt is CLKIN0 input must work in both bipolar and MOS mode. But in my case for Bipolar mode I'm not getting the proper signal and in MOS mode it's working Fine.

    As per the above image this was my CLKIN0 Input

    Case A: CLKIN0 Input Bipolar Mode (Pulse):-

    The above image represents the output of SYSREF signal, some glitch is coming.

    Case B: CLKIN0 Input MOS Mode (Pulse):-

     

    Case C: CLKIN0 Without Input Bipolar mode :-

    The Above image represents the output of SYSREF signal.

    So let me know why LMK is generating output even though there is no input clock fed.It occurs only in bipolar mode.Why?

  • Hi Thanajushree,

    Are you using two PLL loops? If so, then that is the reason that there is an output even if the LMK is not fed an input signal. 

    The second loop is driven by the output of a VCXO, which should be input through OSCin. It is possible for PLL2 to lock without an input to PLL1. That is likely the reason you are seeing an output with no input reference.

    Furthermore, it makes sense that you are only seeing a signal when using MOS mode, as your input is single-ended. MOS mode is more advantageous with a single-ended input.

    Thanks,

    Michael