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LMK04821: Zero Delay Mode not working

Ralf Rascher
Prodigy 35 points

Part Number: LMK04821

Hi all,

I have problems with the Zero Delay Mode for an LMK04821. We use our own

custom made board, set up all the registers using TICS Pro. Both PLLs lock,

but when I compare the input and output frequency I can see the phase between

the two clock is not always aligned. This happens about 2 out of 5 times

I have attached the register settings.

 

Ralf

 

HexRegisterValues.txt 

  • 0
    TI__Genius 13010 points

    Hi Ralf,

    The hex register values typically do not import the correct frequency settings - when I look at your configuration, I see that PLL2 VCO is a frequency that is in neither the VCO0 or VCO1 frequency range. Can you share what your input frequency is?

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    Prodigy 35 points

    Hi Michael,

    regarding the clock frequencies. The main input clock is 100 MHz on clkin0. The external VCXO frequency is also 100 MHz.

  • 0 in reply to Ralf Rascher
    TI__Genius 13010 points

    Hi Ralf,

    Can you share which clock output you are comparing with the input? 

    Furthermore, is there a reason you have all of your SYNC_DISx bits set? This will result in no phase alignment taking place following a SYNC event.

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    Prodigy 35 points

    Hi Michael,

    I compare the clocks on clkin0 (Pin 37) with Dclkout12 (Pin 62).

    I use a SPI command to synchronise the outputs, but I have to admit 

    I do not fully understand the synchronization routing regarding

    the SYNC_DISx bits and if they are relevant for the DCLKOUTs.

    I attached the the register settings for my synchronisation part,

    maybe I do it wrong.

    Fullscreen init_lmk04821.txt Download 
    //Initialise clock synthesiser LMK04821...
R0     0x000000
R2     0x000200
R256   0x010005
R257   0x010155
R258   0x010255
R259   0x010300
R260   0x010420
R261   0x010500
R262   0x010600
R263   0x010766
R264   0x010805
R265   0x010955
R266   0x010A55
R267   0x010B00
R268   0x010C20
R269   0x010D00
R270   0x010E00
R271   0x010F66
R272   0x011005
R273   0x011155
R274   0x011255
R275   0x011300
R276   0x011420
R277   0x011500
R278   0x011600
R279   0x011766
R280   0x011814
R281   0x011955
R282   0x011A55
R283   0x011B00
R284   0x011C00
R285   0x011D00
R286   0x011E71
R287   0x011F00
R288   0x012005
R289   0x012155
R290   0x012255
R291   0x012300
R292   0x012420
R293   0x012500
R294   0x012600
R295   0x012766
R296   0x012814
R297   0x012955
R298   0x012A55
R299   0x012B00
R300   0x012C20
R301   0x012D00
R302   0x012E00
R303   0x012F11
R304   0x013014
R305   0x013155
R306   0x013255
R307   0x013300
R308   0x013400
R309   0x013500
R310   0x013601
R311   0x013701
R312   0x013800
R313   0x013902
R314   0x013A00
R315   0x013B28
R316   0x013C00
R317   0x013D00
R318   0x013E00
R319   0x013F09
R320   0x014002
R321   0x014117
R322   0x014200
R323   0x014393
R324   0x01447F
R325   0x01457F
R326   0x014608
R327   0x01470E
R328   0x014801
R329   0x014942
R330   0x014A03
R331   0x014B16
R332   0x014C00
R333   0x014D00
R334   0x014E00
R335   0x014F7F
R336   0x015003
R337   0x015102
R338   0x015200
R339   0x015300
R340   0x015464
R341   0x015500
R342   0x015664
R343   0x015700
R344   0x015864
R345   0x015900
R346   0x015A64
R347   0x015B17
R348   0x015C2F
R349   0x015DFF
R350   0x015E06
R351   0x015F0B
R352   0x016000
R353   0x016101
R354   0x016224
R355   0x016300
R356   0x016400
R357   0x016501
R369   0x0171AA
R370   0x017202
R371   0x017300
R372   0x017400
R380   0x017C15
R381   0x017D33
R358   0x016600
R359   0x016700
R360   0x016804
R361   0x016959
R362   0x016A3F
R363   0x016BFF
R364   0x016C00
R365   0x016D00
R366   0x016E13
R8189  0x1FFD00
R8190  0x1FFE00
R8191  0x1FFF00

// Generate SYNC pulse
R323   0x014313

// read back PLL1 and PLL2 locked
R386   0x018203
R387   0x018303
R386   0x018202
R387   0x018302

// SYNC sysref clocks
R324   0x014468
R324   0x01447F

  • 0 in reply to Ralf Rascher
    TI__Genius 13010 points

    Hi Ralf,

    That is good info! Thank you for sharing. Can you try setting SYNC_1SHOT_EN to 1 and setting all of the SYNC_DISx bits to 0? That way, your SYNC pin becomes edge sensitive, rather than level sensitive, and the divider reset condition can be cleared automatically following a rising edge on the SYNC pin - meaning that the zero delay portion of the circuit will not be impacted. Furthermore, setting the SYNC_DISx bits to 0 means that you are enabling the SYNC functionality on the corresponding CLKoutX channel. Having SYNC_DISx set to 1 means that a SYNC event will not phase-align the corresponding channel.

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    Prodigy 35 points

    Hi Michael,

    that was it. Setting SYNC_1SHOT_EN to 1 and SYNC_DISx to 0 solved the problem. I tried it with a few boards and the chips

    always synchronize and the input and output clocks are in phase.

    Thanks for your help,

    Ralf