LMK04808: LMK04808BISQ/NOPB - Clock input query

Hi Michael,

We have a single clock input source from an Oven-Controlled Crystal Oscillator (OCXO) connected to the OSCIN pin. Please confirm if this configuration is sufficient to generate 12 output clocks along with 2 OSC_OUT signals.

Also, kindly confirm the maximum input current and power requirements for this clock generator IC.

Regards,
Vinay 

Hi Vinay,

Sorry for the delay. Your OCXO connected to OSCin will be sufficient. 

The maximum input current for a clock input is 5mA.

Thanks,

Michael

Hi Michael,

Please share the user manual or programming procedure for configuring different clock outputs.
Also, kindly confirm whether this clock generator supports a 27 MHz clock frequency.

Regards,
Vinay

Hi Vinay,

Please consult section 8.5.2 Recommended Programming Sequence in the datasheet for the programming sequence. 

Furthermore, this clock generator can support a 27MHz clock frequency (I am assuming you are talking about the input. If you are talking about the output, then the same holds true, but you must ensure that you have an appropriate clock tree to output such a frequency).

Thanks,

Michael

Hi Michael,

If the external oscillator does not have a VC (Voltage Control) input pin, how should the CPout1 pin from the clock generator be terminated?
Should the CPout1 pin be left open, or should it be connected to the voltage control input of the external oscillator (if available)?

Please confirm the recommended termination method when the external oscillator does not support voltage control functionality.

Regards,
Vinay

Hi Vinay,

A VCXO is what is required for this PLL to function properly. An OCXO does not accept a Vtune input, meaning that its output cannot be phase linked to the input (the output of PFD1). An OCXO may be used as a reference, but a VCXO or external crystal with a varactor diode is required in order to make the dual loop configuration work.

This is, of course, assuming you are using dual loop mode. If you are using single loop mode and are inputting the OCXO as the reference, then you may leave CPout1 floating. 

Thanks,

Michael

Hi Michael,

Thanks for the information,

The datasheet does not provide details on LVCMOS clock output termination. Kindly suggest the recommended termination method for the CMOS-type clock output that is interfaced to the ADC clock input.

Regards,
Vinay

Hi Vinay, 

No particular termination is required for the LVCMOS clock output. Assuming that the input to the device is appropriately terminated, no termination is needed for an LVCMOS output (other than a 50Ohm output trace that leads into a high impedance load, do not try to drive these outputs without a load on the end, as this will draw too much current).

Thanks,

Michael

Hi Michael

Please review the attached schematics and advise if any changes are required in the design.

Regards,
VinayLMK_DESIGN.pdf

Hi Vinay,

I took a look over your schematic and I am a bit confused. Are you planning on using this device in a single or dual loop configuration? Dual loop offers the ability to jitter clean, whereas single loop can be used for more direct signal distribution through the VCO.

You cannot input the OCXO to OSCin if you want to use dual loop mode - in this use case, CPout1 needs to be connected to the Vtune pin of a VCXO, and the output of that VCXO needs to be connected to the OSCin pins. If you are using this device in single-loop mode, then there is no need for the loop filter at CPout1, and that pin may be left floating. 

Furthermore, your loop filters appear to have rather generic values. This is fine for now, but if you know what your clock tree is, then you can use the PLLatinum Sim tool to calculate the appropriate loop filter bandwidths to optimize the jitter. 

Everything else looks good.

Thanks,

Michael

Hi Michael,

We need a single clock input with jitter-cleaning. Can an OCXO be used as the LMK’s CLK_IN? Does the LMK accept a VCXO as its reference input? Alternatively, if we feed only a VCXO into OSCIN, can the LMK be configured to generate all 12 outputs?

LMK_DESIGN_2.pdf

Attached the updated schematic design. Please confirm any changes need to be done.

Regards,
Vinay

Hi Vinay,

You can use the OCXO as the LMK's CLKin. Using a VCXO as the reference input is not how the device is intended to be used, since the Vtune pin is therefore not connected to anything that actually steers the device output. 

With a reference as stable as an OCXO, you likely do not need to jitter clean. That can be input to the OSCin pin, and the LMK can still generate all 12 outputs.

Thanks,

Michael

Hi Michael,

If an OCXO is connected to OSCIN, the device will operate in a single-loop configuration. What jitter performance can we expect in this single-loop mode, and can you confirm we should proceed with the initial schematic that uses a single OCXO as the LMK input?

Selected OCXO has maximum jitter of 0.3ps.

7026.LMK_DESIGN.pdf

Regards,
Vinay

Hi Michael,

We have one more option with VCOCXO oscillator having Voltage tuning option.

Can this device be connected to the OSCIN pin of the LMK IC as the primary clock input source? In this case, can the CLKIN0 and CLKIN1 pins be left floating since only a single clock source is required?

Additionally, please confirm whether using a single VCOCXO input to the OSCIN pin and connecting Cpout1 pin to the VC pin (with CLKIN pins left unconnected) will configure the LMK IC to operate in single-loop or dual-loop mode.

VCOCXO Part Number: DOCAT052V-020.0M 
with 0.35ps phase jitter.

Regards,
Vinay

Hi Vinay,

vinay kumar said:

Can this device be connected to the OSCIN pin of the LMK IC as the primary clock input source? In this case, can the CLKIN0 and CLKIN1 pins be left floating since only a single clock source is required?

This device must receive the output of the charge pump of PLL1. If you are using this in a dual loop configuration with the OCXO feeding into the CLKin0, then that will work. Otherwise, I would recommend inputting the OCXO signal into OSCin and using this device in a single-loop configuration (I looked over your schematic and it looks good, but you should depopulate the loop filter at CPout1). I can provide a jitter estimate if you can provide the input frequency of the OCXO, your phase detector frequency, your VCO frequency, and your output frequencies.

Thanks,

Michael

Hi Michael,

Please confirm whether CLOCK IN0 and CLOCK IN1 can remain unconnected when only the OCXO is used as the input to the OSCIN pin.

Regards,
Vinay

Hi Vinay,

This is acceptable, so long as you are operating in single-loop mode.

Thanks,

Michael