LMK00308: Bias VCM in different output

Yuxi Liu(Tony)

Part Number: LMK00308

Hi TIer

Currently , I have a pair of LVDS to the CLKIN/P0 (16 and 17 pins) of the LMK00308SQE clock chip, measured with a differential probe after the capacitance (C709_2/C710_2) was straightened, and found that the Vcm was not at 0v level, with bias, See Figure

The bias is about 0.25V, do you think this is a problem? Is it related to the VCMD parameter in the datasheet? Please give me some advice Thank you

5 days ago

0 Yuxi Liu(Tony) 4 days ago

TI__Expert 3340 points

add the waveform

0 Michael Srinivasan 4 days ago in reply to Yuxi Liu(Tony)

TI__Genius 10200 points

Hi Tony,

I will get to you tomorrow.

Thanks,

Michael

0 Michael Srinivasan 3 days ago in reply to Michael Srinivasan

TI__Genius 10200 points

Hi Tony,

The CLK inputs have an internal bias. This is crucial to the long term performance of the receiver, because the absolute maximum ratings state that the minimum voltage that the device can take as an input is -0.3V. The common mode voltage of 0.25V is perfect, because with an 800mV differential swing, the lowest that either pin will see is -0.15V. I do not see any issue here.

Thanks,

Michael

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LMK00308: Bias VCM in different output