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LMK5B33414: LMK5B33414 - issue with 1PPS Input & output

Guillaume Gauthier
Prodigy 15 points

Part Number: LMK5B33414

Hello, I have some issues configuring my LMK5B33414 with 1PPS Input and output.

My goal is to use the jitter-cleaner function to read the 1PPS input and to integrate it to have a 1PPS output "cleaned" from its natural jitter. How can I manage this ?

I already have a configuration using PLL1 and PLL2 (so only PLL3 is usable) and outputs 0 to 3 and 8 to 13 are already used. I have a input XO of 25MHz (50ppm) and a REF0 input of 48MHz. I want to plug the 1PPS into IN1/REF1 input.

If my configuration is blocking the 1PPS output I can modify it, I just want to have a configuration that allows me a jitter-cleaner function for the 1PPS. A basic example will work just fine.

Please find attached my TICS Pro configuration file that already give me a 1PPS output, but it is not synchronized with the 1PPS input and not jitter-cleaned
Best regards

.LMK5B33141_Test_1PPS_out4_out5.tcs

  • 0
    TI__Genius 17025 points

    Hi Guillaume, 

    One thing to keep in mind is that the relationship between the APLL reference (XO input pin) frequency and the VCO frequency must be fractional to avoid integer boundary spurs and allow the DPLL to servo the APLL numerator without railing off. Otherwise, the DPLL may never lock or the lock may become unstable.

    Since you have a 25 MHz XO input clock, then that is an issue for the BAW APLL which is centered at 2500 MHz. The BAW APLL or APLL3 has the best performance and is recommended to get the lowest jitter possible. Are you able to use another XO input frequency?

    Regards,

    Jennifer

  • 0 in reply to Jennifer Bernal
    Prodigy 15 points

    Hello,
    Yes, this could be possible for us to have another XO frequency.
    I currently have a LMK5B33414EVM to test my 1PPS un-jittered functionnality and I can easily switch to an other XO Frequency (for example 48MHz)

  • 0 in reply to Guillaume Gauthier
    TI__Genius 17025 points

    Hi Guillaume,

    Yes please try with the 48 MHz as that is what is on the EVM and is the commonly tested frequency we use in lab. Besides, the 48 MHz allows for a higher phase detector frequency which reduces APLL noise.

    Let me know if you have further issues.

    Regards,

    Jennifer

  • 0 in reply to Jennifer Bernal
    Prodigy 15 points

    Hello, I tried with 48MHz XO frequency and I had trouble to lock the DPLL3. Can you validate the setup in my attached TICS PRO configuration file ?
    Can you also confirm that when LOPL_DPLL3, LOFL_DPLL3 and HLDOVR3 are all unset this means that my input 1PPS is used for DPLL3 and OUT0 signal generation ? 
    Also I would like to use the ZDM feature (I switched the outputs to use OUT0/OUT1 to output my 1Hz 1PPS signal) to have the lowest jitter possible for my 1PPS output, is this possible with this configuration ? 


    LMK5B33414_1PPS_out0-1_XO_48MHz.tcs